DS100BR111A_15 Datasheet, PDF (9/51 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 1-Lane Repeaters with Input Equalization and Output De-Emphasis

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DS100BR111A
SNLS400D – JANUARY 2012 – REVISED JANUARY 2015
7.6 Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
PARAMETER
TEST CONDITIONS
MIN
SERIAL BUS INTERFACE DC SPECIFICATIONS⁽¹⁾
V_IL
Data, Clock Input Low Voltage
V_IH
Data, Clock Input High Voltage
2.1
I_PULLUP
Current Through Pull-Up Resistor High Power Specification
or Current Source
4
V_DD
I_LEAK-Bus
C_I
R_TERM
Nominal Bus Voltage
Input Leakage Per Bus Segment See ⁽²⁾
Capacitance for SDA and SCL
See ^{(2) (3) (4)}
External Termination Resistance Pullup V_DD = 3.3 V, See ^{(2) (3) (5)}
pull to V_DD = 2.5V ± 5% OR 3.3V ±
10%
Pullup V_DD = 2.5 V, See ^{(2) (3) (5)}
2.375
-200
SERIAL BUS INTERFACE TIMING SPECIFICATIONS
ENSMB = VDD (Slave Mode)
FSMB
Bus Operating Frequency
ENSMB = Float (Master Mode) ⁽¹⁾
280
T_BUF
Bus Free Time Between Stop and
Start Condition
1.3
T_HD:STA
Hold time after (Repeated) Start At I_PULLUP, Max
Condition. After this period, the
0.6
first clock is generated.
T_SU:STA
Repeated Start Condition Setup
Time
0.6
T_SU:STO
Stop Condition Setup Time
0.6
T_HD:DAT
Data Hold Time
0
T_SU:DAT
Data Setup Time
100
T_LOW
Clock Low Period
1.3
T_HIGH
Clock High Period
See ⁽⁶⁾
0.6
t_F
Clock/Data Fall Time
See ⁽⁶⁾
t_R
Clock/Data Rise Time
See ⁽⁶⁾
t_POR
Time in which a device must be
operational after power-on reset
See ^{(4) (6)}
TYP
2000
1000
400
MAX UNIT
0.8
V
3.6
V
mA
3.6
V
200
µA
10
pF
Ω
Ω
400 kHz
520 kHz
µs
µs
µs
µs
ns
ns
µs
50
µs
300
ns
300
ns
500 ms
(1) EEPROM interface requires 1 MHz capable EEPROM device.
(2) Recommended value.
(3) Recommended maximum capacitance load per bus segment is 400 pF.
(4) Guaranteed by design and characterization. Parameter not tested in production.
(5) Maximum termination voltage should be identical to the device supply voltage.
(6) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
7.7 Timing Requirements — LOS and ENABLE / DISABLE Timing
T_{LOS_OFF}
T_{LOS_ON}
T_OFF
T_ON
T_{LP_EXIT}
T_{LP_ENTER}
Input IDLE to Active
RX_LOS response time
Input Active to IDLE
RX_LOS response time
TX Disable assert Time
TX_DIS = HIGH to Output OFF
TX Disable negateTime
TX_DIS = Low to Output ON
Auto Low Power Exit
ALP to Normal Operation
Auto Low Power Enter
Normal Operation to Auto Low Power
See ⁽¹⁾
See ⁽¹⁾
See ⁽¹⁾
See ⁽¹⁾
See ⁽¹⁾
See ⁽¹⁾
MIN NOM
0.035
MAX UNIT
µs
0.4
µs
0.005
µs
0.150
µs
150
ns
100
µs
(1) Parameter not tested in production.
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