DS100BR111A_15 Datasheet, PDF (42/51 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 1-Lane Repeaters with Input Equalization and Output De-Emphasis

DS100BR111A
SNLS400D – JANUARY 2012 – REVISED JANUARY 2015
10 Power Supply Recommendations
www.ti.com
10.1 3.3-V or 2.5-V Supply Mode Operation
The DS100BR111A has an optional internal voltage regulator to provide the 2.5 V supply to the device. In 3.3 V
mode, the VIN pin = 3.3 V is used to supply power to the device and the VDD pins should be left open. The
internal regulator will provide the 2.5 V to the VDD pins of the device and a 0.1 μF cap is needed at each of the
two VDD pins for power supply de-coupling (total capacitance should be ≤ 0.2 μF). The VDD_SEL pin must be
tied to GND to enable the internal regulator. In 2.5 V mode, the VIN pin should be left open and 2.5 V supply
must be applied to the VDD pins. The VDD_SEL pin must be left open (no connect) to disable the internal
regulator.
The DS100BR111A can be configured for 2.5 V operation or 3.3 V operation. The lists below outline required
connections for each supply selection.
3.3 V Mode of Operation
• Tie VDD_SEL =GND.
• Feed 3.3 V supply into VIN pin. Local 10 µF and 1 µF decoupling at VIN is recommended.
• See information on VDD bypass in Power Supply Bypass.
• SDA and SCL pins should connect pull-up resistor to VIN.
• Any 4-Level input which requires a connection to "Logic 1" should use a 1 kΩ resistor to VIN.
2.5 V Mode of Operation
• VDD_SEL = Float
• VIN = Float
• Feed 2.5 V supply into VDD pins. Local 10 µF and 1 µF decoupling at VDD is recommended.
• See information on VDD bypass in Power Supply Bypass.
• SDA and SCL pins connect pull-up resistor to VDD for 2.5 V or 3.3 V microcontroller SMBus IO.
• Any 4-Level input which requires a connection to "Logic 1" should use a 1 kΩ resistor to VDD.
NOTE
The DAP (bottom solder pad) is the GND connection.
3.3 V mode
Enable
VDD_SEL
Internal
voltage
regulator
2.5 V
VIN
VDD
VDD
2.5 V mode
3.3 V
Capacitors can be
either tantalum or an
ultra-low ESR ceramic.
0.1 µF
0.1 µF
Disable
VDD_SEL
open
Internal
voltage
regulator
VIN
open
VDD
0.1 µF
2.5 V
VDD
0.1 µF
Capacitors can be
either tantalum or an
ultra-low ESR ceramic.
Place 0.1 µF capacitors close to VDD Pins
Total capacitance should be % 0.2 µF
Place 0.1 µF capacitors close to VDD Pins
Figure 39. 3.3 V or 2.5 V Supply Connection Diagram
42
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DS100BR111A