DS100BR111A_15 Datasheet, PDF (13/51 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 1-Lane Repeaters with Input Equalization and Output De-Emphasis

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DS100BR111A
SNLS400D – JANUARY 2012 – REVISED JANUARY 2015
8.3 Feature Description
The 4-level input pins use a resistor divider to set the four valid control levels and provide a wider range of
control settings when ENSMB = 0. There is an internal 30 kΩ pull-up and a 60 kΩ pull-down connected to the
package pin. These resistors, together with the external resistor connection, combine to achieve the desired
voltage level. By using the 1 kΩ pull-down, 20 kΩ pull-down, no connect, or 1 kΩ pull-up, the optimal voltage
levels for each of the four input states are achieved as shown in Table 1.
Table 1. 4–Level Control Pin Settings
LEVEL
0
R
F
1
SETTING
Tie 1 kΩ to GND
Tie 20 kΩ to GND
Float (leave pin open)
Tie 1 kΩ to V_IN or V_DD
RESULTING PIN VOLTAGE
3.3 V MODE
2.5 V MODE
0.10 V
0.08 V
1/3 x V_IN
2/3 x V_IN
V_IN - 0.05 V
1/3 x V_DD
2/3 x V_DD
V_DD - 0.04 V
8.3.1 Typical 4-Level Input Thresholds
• Internal Threshold between 0 and R = 0.2 * V_IN or V_DD
• Internal Threshold between R and F = 0.5 * V_IN or V_DD
• Internal Threshold between F and 1 = 0.8 * V_IN or V_DD
In order to minimize the startup current associated with the integrated 2.5 V regulator, the 1 kΩ pull-up / pull-
down resistors are recommended. If several four level inputs require the same setting, it is possible to combine
two or more 1 kΩ resistors into a single lower value resistor. As an example, combining two inputs with a single
500 Ω resistor is a valid way to save board space.
8.4 Device Functional Modes
8.4.1 Pin Control Mode
When in Pin Mode (ENSMB = 0), equalization, de-emphasis, and VOD (output amplitude) can be selected via
external pin control for both the A-channel and B-channel. Equalization and de-emphasis can be programmed by
pin selection for each side independently. For further device control, the VOD_SEL and MODE pins are available
to improve DS100BR111A performance depending on design applications. The receiver electrical idle detect
threshold is also adjustable via the SD_TH pin. Pin control mode is ideal in situations where neither MCU or
EEPROM is available to access the device via SMBus SDA and SCL lines.
8.4.2 SMBus Slave Mode
When in Slave SMBus Mode (ENSMB = 1), equalization, de-emphasis, and VOD (output amplitude) are all
programmable on an individual channel basis. Upon assertion of ENSMB, the EQx, DEMx, and VODx settings
are controlled by SMBus immediately. It is important to note that SMBus settings can only be changed from their
defaults after asserting Register Enable by setting Reg 0x06[3] = 1. The EQx, DEMx, and VODx pins are
subsequently converted to AD0-AD3 SMBus address inputs. The other external control pins (TX_DIS, MODE,
and SD_TH) remain active unless their respective registers are written to and the appropriate override bit is set.
If the user overrides a pin control, the input voltage level of that control pin is ignored until ENSMB is driven low
(Pin Mode). In the event that channels are powered down via the TX_DIS pin, register setting states are not
affected.
Table 2. Signal Detect Threshold Level⁽¹⁾
Level
1
2
3
4
SD_TH (Pin 14)
0
R
F (Default)
1
SMBus REG bit
[3:2] and [1:0]
10
01
00
11
TYPICAL ASSERT LEVEL
(mVpp)
210
160
180
190
TYPICAL DE-ASSERT LEVEL
(mVpp)
150
100
110
130
(1) Typical assert and de-assert levels were measured with VDD = 2.5 V, 25°C, and 010101 pattern at 8 Gbps.
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