DS100BR111A_15 Datasheet, PDF (7/51 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 1-Lane Repeaters with Input Equalization and Output De-Emphasis

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DS100BR111A
SNLS400D – JANUARY 2012 – REVISED JANUARY 2015
Electrical Characteristics (continued)
PARAMETER
LVCMOS DC SPECIFICATIONS
V_IH25
High Level Input Voltage,
2-Level LVCMOS
V_IH33
High Level Input Voltage,
2-Level LVCMOS
V_IL
Low Level Input Voltage,
2-Level LVCMOS
V_OH
High Level Output Voltage
V_OL
Low Level Output Voltage
I_IN
Input Leakage Current
I_IN-P
Input Leakage Current
4-Level Input ⁽²⁾
CML RECEIVER INPUTS
V_TX
Source Transmit Launch
Differential Signal Level
RL_RX-IN
RX return loss
HIGH SPEED TRANSMITTER OUTPUTS
V_OD1
Output Voltage Differential Swing
V_OD2
Output Voltage Differential Swing
V_OD3
Output Voltage Differential Swing
V_{OD_DE1}
De-Emphasis Levels
V_{OD_DE2}
De-Emphasis Levels
TEST CONDITIONS
2.5 V Supply Mode
3.3 V Supply Mode
I_OH = -4.0 mA ⁽¹⁾
I_OL = 4.0 mA
Vinput = 0 V or VDD
VDD_SEL = Float
Vinput = 0 V or VIN
VDD_SEL = Low
Vinput = 0 V or VDD - 0.05 V
VDD_SEL = Float
Vinput = 0 V or VIN - 0.05 V
VDD_SEL = Low
Default power-up conditions
ENSMB = 0 or 1
SDD11 @ 4.1 GHz
SDD11 @ 11.1 GHz
SCD11 @ 11.1 GHz
OUT+ and OUT- AC coupled and
terminated by 50 Ω to GND
VOD_SEL = Low (575 mVpp setting)
DE = Low
OUT+ and OUT- AC coupled and
terminated by 50 Ω to GND
VOD_SEL = Float (850 mVpp setting)
DE = Low
OUT+ and OUT- AC coupled and
terminated by 50 Ω to GND
VOD_SEL = 20 kΩ to GND (1050
mVpp)
DE = Low
OUT+ and OUT- AC coupled and
terminated by 50 Ω to GND
VOD_SEL = Float (850 mVpp)
DE = Float
OUT+ and OUT- AC coupled and
terminated by 50 Ω to GND
VOD_SEL = Float (850 mVpp)
DE = 20 kΩ to GND
MIN
TYP
MAX UNIT
2.0
2.0
GND
2.0
-15
-15
VDD
V
VIN
V
0.7
V
V
0.4
V
15
µA
15
-160
80
µA
190
800
1600 mVp-p
-12
-8
dB
-10
425
575
725
675
850
1025 _mVp-p
850
1050
1275
-3.5
dB
-6
dB
(1) VOH only applies to the DONE pin; LOS, SCL, and SDA are open-drain outputs that have no internal pull-up capability. DONE is a full
LVCMOS output with pull-up and pull-down capability.
(2) Input is held to a maximum of 50 mV below VDD or VIN to simulate the use of a 1 kΩ resistor on the input.
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