DS100BR111A_15 Datasheet, PDF (18/51 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 1-Lane Repeaters with Input Equalization and Output De-Emphasis

DS100BR111A
SNLS400D – JANUARY 2012 – REVISED JANUARY 2015
www.ti.com
8.5.6.1 Master EEPROM Programming
Below is an example of a 2 kbits (256 x 8-bit) EEPROM in hex format for the DS100BR111A device. The first 3
bytes of the EEPROM always contain a header common and necessary to control initialization of all devices
connected to the same SMBus line. There is a CRC enable flag to enable or disable CRC checking. There is a
MAP bit to flag the presence of an address map that specifies the configuration data start address in the
EEPROM. If the MAP bit is not present, the configuration data start address immediately follows the 3-byte base
header. A bit to indicate an EEPROM size > 256 bytes is necessary to address the EEPROM properly. There are
37 bytes of data size for each DS100BR111A device. For more details about EEPROM programming and Master
mode, refer to SNLA228.
1 :1000000000002000000407002FED4002FED4002FC4
2 :10001000AD4002FAD400005F568005F5A8005F5AE9
3 :100020008005F5A800005454F100000000000000A8
4 :1000300000000000000000000000000000000000C0
5 :1000400000000000000000000000000000000000B0
6 :1000500000000000000000000000000000000000A0
7 :100060000000000000000000000000000000000090
8 :100070000000000000000000000000000000000080
9 :100080000000000000000000000000000000000070
10 : 1 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0
11 : 1 0 0 0 A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0
12 : 1 0 0 0 B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0
13 : 1 0 0 0 C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0
14 : 1 0 0 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0
15 : 1 0 0 0 E 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
16 : 1 0 0 0 F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17 : 0 0 0 0 0 0 0 1 F F
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CRC-8 based on 40 bytes of
data in this shaded area
CRC Polynomial = 0x07
Insert the CRC value here
MAX EEPROM Burst = 32
Figure 8. Typical EEPROM Data Set
NOTE
The maximum EEPROM size supported is 8 kbits (1024 x 8 bits).
The CRC-8 calculation is performed for each device on the first 3 bytes of header information plus the 37 bytes
of data for the DS100BR111A or 40 bytes in total. The result of this calculation is placed immediately after the
DS100BR111A data in the EEPROM which ends with "5454". The CRC-8 in the DS100BR111A uses a
polynomial = x⁸ + x² + x + 1.
There are two pins that provide unique functions in SMBus Master mode:
• DONE
• READEN
When the DS100BR111A is powered up in SMBus Master mode, it reads its configuration from the external
EEPROM when the READEN pin goes low. When the DS100BR111A is finished reading its configuration from
the external EEPROM, it drives the DONE pin low. In applications where there is more than one DS100BR111A
on the same SMBus, bus contention can result if more than one DS100BR111A tries to take control of the
SMBus at the same time. The READEN and DONE pins prevent this bus contention. The system should be
designed so that the READEN pin from one DS100BR111A in the system is driven low on power-up. This
DS100BR111A will take command of the SMBus on power-up and will read its initial configuration from the
external EEPROM. When the first DS100BR111A is finished reading its configuration, it will drive the DONE pin
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