DS100BR111A_15 Datasheet, PDF (43/51 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 1-Lane Repeaters with Input Equalization and Output De-Emphasis

www.ti.com
DS100BR111A
SNLS400D – JANUARY 2012 – REVISED JANUARY 2015
10.2 Power Supply Bypass
Two approaches are recommended to ensure that the DS100BR111A is provided with an adequate power
supply bypass. First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on
adjacent layers of the printed circuit board. Second, careful attention to supply bypassing through the proper use
of bypass capacitors is required. A 0.1 μF bypass capacitor should be connected to each VDD pin such that the
capacitor is placed as close as possible to the device. Small body size capacitors (such as 0402) reduce the
capacitors' parasitic inductance and also help in placement close to the VDD pin. If possible, the layer thickness
of the dielectric should be minimized so that the VDD and GND planes create a low inductance supply with
distributed capacitance.
11 Layout
11.1 Layout Guidelines
The differential inputs and outputs are designed with 100 Ω differential terminations. Therefore, they should be
connected to interconnects with controlled differential impedance of approximately 85-110 Ω. It is preferable to
route differential lines primarily on one layer of the board, particularly for the input traces. The use of vias should
be avoided if possible. If vias must be used, they should be used sparingly and must be placed symmetrically for
each side of a given differential pair. Whenever differential vias are used, the layout must also provide for a low
inductance path for the return currents as well. Route the differential signals away from other signals and noise
sources on the printed circuit board. To minimize the effects of crosstalk, a 5:1 ratio or greater should be
maintained between inter-pair spacing and trace width. See AN-1187 “Leadless Leadframe Package (LLP)
Application Report” (literature number SNOA401) for additional information on QFN (WQFN) packages.
The DS100BR111A pinout promotes easy high speed routing and layout. To optimize DS100BR111A
performance, refer to the following guidelines:
1. Place local VIN and VDD capacitors as close as possible to the device supply pins. Often the best location is
directly under the DS100BR111A pins to reduce the inductance path to the capacitor. In addition, bypass
capacitors may share a via with the DAP GND to minimize ground loop inductance.
2. Differential pairs going into or out of the DS100BR111A should have adequate pair-to-pair spacing to
minimize crosstalk.
3. Use return current via connections to link reference planes locally. This ensures a low inductance return
current path when the differential signal changes layers.
4. Optimize the via structure to minimize trace impedance mismatch.
5. Place GND vias around the DAP perimeter to ensure optimal electrical and thermal performance. A 2x2 or
3x3 array of GND vias for the DAP is recommended.
6. Use small body size AC coupling capacitors when possible — 0402 or smaller size is preferred. The AC
coupling capacitors should be placed closer to the Rx on the channel.
11.2 Layout Example
In most cases, DS100BR111A layouts will fit neatly into a 1-lane application. The example layout in Figure 40
shows the DS100BR111A channels in a typical 1-lane bidirectional layout.
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DS100BR111A
Submit Documentation Feedback
43