DS100BR111A_15 Datasheet, PDF (5/51 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 1-Lane Repeaters with Input Equalization and Output De-Emphasis

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DS100BR111A
SNLS400D – JANUARY 2012 – REVISED JANUARY 2015
Pin Functions⁽¹⁾ (continued)
PIN
NAME
SD_TH
VDD_SEL
POWER
VDD
VIN
GND
NUMBER
14
16
21, 22
15
DAP
I/O, TYPE
DESCRIPTION
I, 4-LEVEL,
LVCMOS
I, FLOAT
The SD_TH pin controls LOS threshold setting
Assert (mVpp), Deassert (mVpp)
High = 190 mVpp, 130 mVpp
Float = 180 mVpp, 110 mVpp (Default)
20 kΩ to GND = 160 mVpp, 100 mVpp
1 kΩ to GND = 210 mVpp, 150 mVpp⁽⁵⁾
Enables the 3.3 V to 2.5 V internal regulator
Low = 3.3 V Operation
Float = 2.5 V Operation
Power
Power
Power
Power supply pins
When in 2.5 V mode, connect to 2.5 V supply.
When in 3.3 V mode, do not connect to any supply voltage. Should be used to attach
external decoupling to device, 100 nF recommended.
See Power Supply Recommendations for additional information.
VIN = 3.3 V ± 10% (input to internal LDO regulator)
When in 2.5 V mode, VIN pin must be left floating.
See Power Supply Recommendations for additional information.
Ground pad (DAP - die attach pad).
(5) Using values less than the default level can extend the time required to detect LOS and are not recommended.
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