DS100BR111A_15 Datasheet, PDF (12/51 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 1-Lane Repeaters with Input Equalization and Output De-Emphasis

DS100BR111A
SNLS400D – JANUARY 2012 – REVISED JANUARY 2015
8 Detailed Description
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8.1 Overview
The DS100BR111A is a high performance bidirectional 1-lane repeater optimized for 10GbE and SAS/SATA
operation, where its programmable equalization and de-emphasis compensate for lossy FR-4 printed circuit
board traces or balanced cables. The DS100BR111A operates in 3 modes: Pin Control Mode (ENSMB = 0),
SMBus Slave Mode (ENSMB = 1), and SMBus Master Mode (ENSMB = Float) to load register information from
external EEPROM.
Each channel has a signal detector circuit that monitors the input signal amplitude. When the input signal level is
below the detector's de-assert level, the output is disabled. When input signal level exceeds the detector's assert
level, the output is enabled. The signal detector circuit is used to support the OOB signaling used in SAS and
SATA.
8.2 Functional Block Diagram
A Channel
Term
Signal
Detect
INA+
INA-
ENSMB
EQA[1:0]
DEMA
VOD_SEL
OUTA+
EQ
Pre-
driver
Driver
OUTA-
READEN
AD[3:0]
SCL
SDA
TX_DIS
VDD_SEL
VIN
Digital Core and SMBus Registers
B Channel
Internal voltage
regulator
Signal Term
Detect
DONE
ENSMB
EQB[1:0]
DEMB
VOD_SEL
OUTB+
Driver
Pre-
driver
EQ
OUTB-
INB+
INB-
Note: This diagram is representative of device signal flow only.
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