DS100BR111A_15 Datasheet, PDF (10/51 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 1-Lane Repeaters with Input Equalization and Output De-Emphasis

DS100BR111A
SNLS400D – JANUARY 2012 – REVISED JANUARY 2015
VOD = [Out+ - Out-]
80%
0V
20%
80%
20%
t_RISE
t_FALL
Figure 1. Output Rise and Fall Transition Times
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IN
0V
t_PLHD
OUT
0V
t_PHLD
Figure 2. Propagation Delay Timing Diagram
+
IN
DATA
0V
-
t_IDLE-DATA
+
t_DATA-IDLE
OUT
DATA
0V
-
IDLE
IDLE
Figure 3. Transmit Idle-Data and Data-Idle Response Time
t_LOW
t_R
t_HIGH
t_BUF
t_HD:STA
t_HD:DAT
t_F
t_SU:DAT
t_SU:STA
t_SU:STO
SP
ST
ST
SP
Figure 4. SMBus Timing Parameters
SCL
SDA
10
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