DS100BR111A_15 Datasheet, PDF (4/51 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 1-Lane Repeaters with Input Equalization and Output De-Emphasis

DS100BR111A
SNLS400D – JANUARY 2012 – REVISED JANUARY 2015
www.ti.com
Pin Functions⁽¹⁾ (continued)
PIN
NAME
NUMBER
I/O, TYPE
DESCRIPTION
ENSMB = Float or 1 (SMBus MODES)
I, 2-LEVEL, Clock output when loading EEPROM configuration, reverting to SMBus clock input
SCL
5
LVCMOS, when EEPROM load is complete (ALL_DONE = 0).
O, Open External 2 kΩ to 5 kΩ pull-up resistor to VDD (2.5 V mode) or VIN (3.3 V mode)
Drain
recommended as per SMBus interface standards⁽²⁾
SDA
I, 2-LEVEL, In both SMBus Modes, this pin is the SMBus data I/O. Data input or open drain output.
4
LVCMOS, External 2 kΩ to 5 kΩ pull-up resistor to VDD (2.5 V mode) or VIN (3.3 V mode)
O, Open recommended as per SMBus interface standards⁽²⁾
Drain
AD0-AD3
10, 9, 2, 1
I, 4-LEVEL,
LVCMOS
ENSMB Master or Slave mode
SMBus Slave Address Inputs. In SMBus mode, these pins are the user set SMBus
slave address inputs. There are 16 addresses supported by these pins.
Pins must be tied Low or HIGH when used to define the device SMBus address. ⁽³⁾
READEN
ENSMB = Float: When using SMBus Master Mode, a logic low on this pin starts the
17
I, 2-LEVEL,
LVCMOS
load from the external EEPROM.
ENSMB = 1: When using SMBus Slave Mode, the VOD_SEL/READEN pin must be
tied Low for the AD[3:0] to be active. If this pin is tied High or left floating, an address
of 0xB0 will be used for the DS100BR111A.
DONE
When using an External EEPROM (ENSMB = Float), Valid Register Load Status
18
O, 2-LEVEL, Output
LVCMOS High = External EEPROM load failed or incomplete
Low = External EEPROM load passed
ENSMB = 0 (PIN MODE)
EQA0, EQA1
EQB0, EQB1
10, 9
1, 2
I, 4-LEVEL,
LVCMOS
EQA[1:0] and EQB[1:0] control the level of equalization on the input pins. EQA[1:0]
controls the A channel, and EQB[1:0] controls the B channel. The pins are only active
when ENSMB = 0.
When ENSMB = 1, the SMBus registers provide independent control of each channel,
and the EQB0/B1 pins are converted to SMBus AD2/AD3 inputs.
See Table 3 for additional information.
DEMA, DEMB
DEMA and DEMB control the level of de-emphasis for the output driver when in 10G
mode. DEMA controls the A channel, and DEMB controls the B channel. The pins are
4, 5
I, 4-LEVEL, only active when ENSMB = 0.
LVCMOS When ENSMB = 1, the SMBus registers provide independent control of each channel,
and the DEM pins are converted to SMBus SCL and SDA pins.
See Table 4 for additional information.
VOD_SEL
VOD Select
High = (VOD = 950 mVpp or 1150 mVpp)
17
I, 4-LEVEL, Float = (VOD = 850 mVpp)
LVCMOS 20 kΩ to GND = (VOD = 1050 mVpp)
1 kΩ to GND = (VOD = 575 mVpp)
See ⁽³⁾⁽⁴⁾ for additional notes. See Table 2 for additional information.
MODE
Controls Device Mode of Operation
High= 10GbE Mode, Continuous Talk (Output Always On)
18
I, 4-LEVEL, Float = Slow OOB
LVCMOS 20 kΩ to GND = eSATA Mode, Fast OOB, Auto Low Power on 100 µs of inactivity. SD
stays active.
1 kΩ to GND = SAS Mode, Fast OOB
CONTROL PINS — BOTH PIN AND SMBus MODES (LVCMOS)
TX_DIS
6
I, 2-LEVEL, High = OUTA Enabled, OUTB Disabled
LVCMOS Low = OUTA and OUTB Enabled
LOS
13
O, Open Indicates Loss of Signal (Default is LOS on INA). Can be modified via SMBus
Drain
registers.
(2) SCL and SDA pins can be tied either to 3.3 V or 2.5 V, regardless of whether the device is operating in 2.5 V mode or 3.3 V mode.
(3) Setting VOD_SEL = High in SMBus Mode will force the SMBus Address = 0xB0
(4) DS100BR111A OUTA is limited to 575 mVpp in pin mode.
4
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DS100BR111A