DS100BR111A_15 Datasheet, PDF (14/51 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 1-Lane Repeaters with Input Equalization and Output De-Emphasis

DS100BR111A
SNLS400D – JANUARY 2012 – REVISED JANUARY 2015
www.ti.com
8.4.3 SMBus Master Mode
When in SMBus Master Mode (ENSMB = Float), the equalization, de-emphasis, and VOD (output amplitude) for
multiple devices can be loaded via external EEPROM. By asserting a Float condition on the ENSMB pin, an
external EEPROM writes register settings to each device in accordance with its SMBus slave address. The
settings programmable by external EEPROM provide only a subset of all the register bits available via SMBus
Slave Mode, and the bit-mapping between SMBus Slave Mode registers and EEPROM addresses can be
referenced in Table 6. Once the EEPROM successfully finishes loading each device's register settings, the
device reverts back to SMBus Slave Mode and releases SDA and SCL control to an external master MCU. If the
EEPROM fails to load settings to a particular device, for example due to an invalid or blank hex file, the device
waits indefinitely in an unknown state where access to the SMBus lines is not possible.
8.4.4 Signal Conditioning Settings
Equalization, de-emphasis, and VOD settings accessible via the pin controls are chosen to meet the needs of
most high speed applications. For additional levels and flexibility in EQ, de-emphasis, and VOD programming,
these settings can be controlled via the SMBus registers. Each control pin input has a total of four possible
voltage level settings. In pin mode, Table 3 shows the 16 EQ settings available, and Table 4 shows the 16 de-
emphasis and VOD combination settings available. Note that when in pin mode, only 16 of a possible 256 EQ
programmable levels can be accessed by setting the EQx[1:0] pins. In addition, each pin setting applied to the
VOD_SEL and DEMx pin input programs a fixed combination of VOD and de-emphasis. In order to access all
256 EQ levels and control both VOD and de-emphasis settings independently, SMBus register access must be
used.
Table 3. Equalizer Settings
LEVEL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
EQA1
EQB1
0
0
0
0
R
R
R
R
F
F
F
F
1
1
1
1
EQA0
EQB0
0
R
F
1
0
R
F
1
0
R
F
1
0
R
F
1
EQUALIZATION BOOST RELATIVE TO DC
EQ — 8 bits [7:0] dB BOOST at 5 GHz
0000 0000 = 0x00
2.5
0000 0001 = 0x01
6.5
0000 0010 = 0x02
9
0000 0011 = 0x03
11.5
0000 0111 = 0x07
14
0001 0101 = 0x15
15
0000 1011 = 0x0B
17
0000 1111 = 0x0F
19
0101 0101 = 0x55
20
0001 1111 = 0x1F
23
0010 1111 = 0x2F
25
0011 1111 = 0x3F
27
1010 1010 = 0xAA
30
0111 1111 = 0x7F
31
1011 1111 = 0xBF
33
1111 1111 = 0xFF
34
SUGGESTED MEDIA⁽¹⁾
FR4 < 5 inch trace
FR4 5 inch trace
FR4 10 inch trace
FR4 15 inch trace
FR4 20 inch trace
FR4 25 inch trace
FR4 25 inch trace
7m 30 AWG Cable
FR4 30 inch trace
8m 30 AWG Cable
FR4 35 inch trace
10m 30 AWG Cable
10m - 12m, Cable
(1) Settings are approximate and will change based on PCB material, trace dimensions, and driver waveform characteristics. Optimal EQ
settings should be determined via simulation and prototype verification.
14
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