DS100BR111A_15 Datasheet, PDF (3/51 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 1-Lane Repeaters with Input Equalization and Output De-Emphasis

www.ti.com
6 Pin Configuration and Functions
RTW Package
24-Lead WQFN
Top View
DS100BR111A
SNLS400D – JANUARY 2012 – REVISED JANUARY 2015
OUTA+ 7
OUTA- 8
AD1/EQA1 9
AD0/EQA0 10
INB+ 11
INB- ₁₂
SMBUS AND
CONTROL
24 INA+
23 INA-
22 _VDD
21 _VDD
20 _OUTB+
19 OUTB-
(1) The center DAP on the package bottom is the device GND connection. This pad must be connected to GND through
multiple (minimum of 4) vias to ensure optimal electrical and thermal performance.
PIN
NAME
NUMBER
DIFFERENTIAL HIGH SPEED I/O's
INA+, INA- ,
INB+, INB-
24, 23
11, 12
OUTA+, OUTA-,
OUTB+, OUTB-
CONTROL PINS
7, 8
20, 19
ENSMB
3
I/O, TYPE
I, CML
O, CML
I, 4-LEVEL,
LVCMOS
Pin Functions⁽¹⁾
DESCRIPTION
Inverting and non-inverting CML differential inputs to the equalizer. On-chip 50 Ω
termination resistors connect both INx+ and INx- to VDD. Compatible with AC coupled
CML inputs.
Inverting and non-inverting 50 Ω driver outputs with de-emphasis. Compatible with AC
coupled CML inputs.
System Management Bus (SMBus) Enable Pin
High = Register Access SMBus Slave Mode
Float = Read External EEPROM (SMBus Master Mode)
Tie 1 kΩ to GND = Pin Mode
(1) LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not guaranteed. Unless
the "Float" level is desired, 4-Level input pins require a minimum 1 kΩ resistor to GND, VDD (in 2.5 V mode), or VIN (in 3.3 V mode).
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DS100BR111A
Submit Documentation Feedback
3