DS100BR111A_15 Datasheet, PDF (16/51 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 1-Lane Repeaters with Input Equalization and Output De-Emphasis

DS100BR111A
SNLS400D – JANUARY 2012 – REVISED JANUARY 2015
www.ti.com
AD[3:0] SETTINGS
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 5. Device Slave Address Bytes
FULL SLAVE ADDRESS BYTE
(7-Bit ADDRESS + WRITE BIT)
B0
B2
B4
B6
B8
BA
BC
BE
C0
C2
C4
C6
C8
CA
CC
CE
7-Bit SLAVE ADDRESS (HEX)
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
The SDA and SCL pins are 3.3 V tolerant, but are not 5 V tolerant. An external pull-up resistor is required on the
SDA and SCL line. The resistor value can be from 2 kΩ to 5 kΩ depending on the voltage, loading, and speed.
8.5.2 Transfer Of Data Via the SMBus
During normal operation, the data on SDA must be stable during the time when SCL is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SCL is High indicates a message START condition.
STOP: A Low-to-High transition on SDA while SCL is High indicates a message STOP condition.
IDLE: If SCL and SDA are both High for a time exceeding t_BUF from the last detected STOP condition or if they
are High for a total exceeding the maximum specification for t_HIGH, then the bus will transfer to the IDLE state.
8.5.3 SMBus Transactions
The device supports WRITE and READ transactions. See Table 9 for register address, type (Read/Write, Read
Only), default value, and function information.
8.5.4 Writing a Register
To write a register, the following protocol is used (see SMBus 2.0 specification):
1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drive the 8-bit data byte.
6. The Device drives an ACK bit (“0”).
7. The Host drives a STOP condition.
Once the WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices
may now occur.
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