LM3S5K36 Datasheet, PDF (845/1050 Pages) Texas Instruments – Stellaris® LM3S5K36 Microcontroller

Stellaris^® LM3S5K36 Microcontroller
USB Receive Control and Status Endpoint 1 High (USBRXCSRH1)
Base 0x4005.0000
Offset 0x117
Type R/W, reset 0x00
7
6
5
4
3
2
1
0
AUTOCL ISO
DMAEN ^{DISNYET /} DMAMOD
PIDERR
reserved
Type R/W
R/W
R/W
R/W
R/W
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
Bit/Field
7
Name
AUTOCL
Type
R/W
Reset
0
Description
Auto Clear
Value Description
0 No effect.
1 Enables the RXRDY bit to be automatically cleared when a packet
of USBRXMAXPn bytes has been unloaded from the receive
FIFO. When packets of less than the maximum packet size are
unloaded, RXRDY must be cleared manually. Care must be taken
when using µDMA to unload the receive FIFO as data is read
from the receive FIFO in 4 byte chunks regardless of the value
of the MAXLOAD field in the USBRXMAXPn register, see “DMA
Operation” on page 795.
6
ISO
R/W
0
Isochronous Transfers
Value Description
0 Enables the receive endpoint for isochronous transfers.
1 Enables the receive endpoint for bulk/interrupt transfers.
5
DMAEN
R/W
0
DMA Request Enable
Value Description
0 Disables the µDMA request for the receive endpoint.
1 Enables the µDMA request for the receive endpoint.
Note:
3 TX and 3 RX endpoints can be connected to the µDMA
module. If this bit is set for a particular endpoint, the DMAARX,
DMABRX, or DMACRX field in the USB DMA Select
(USBDMASEL) register must be programmed
correspondingly.
4
DISNYET / PIDERR R/W
0
Disable NYET / PID Error
Value Description
0 No effect.
1 For bulk or interrupt transactions: Disables the sending of NYET
handshakes. When this bit is set, all successfully received
packets are acknowledged, including at the point at which the
FIFO becomes full.
For isochronous transactions: Indicates a PID error in the
received packet.
January 21, 2012
845
Texas Instruments-Production Data