LM3S5K36 Datasheet, PDF (544/1050 Pages) Texas Instruments – Stellaris® LM3S5K36 Microcontroller

Analog-to-Digital Converter (ADC)
12.4.2
6. If required by the application, reconfigure the sample sequencer priorities in the ADCSSPRI
register. The default configuration has Sample Sequencer 0 with the highest priority and Sample
Sequencer 3 as the lowest priority.
Sample Sequencer Configuration
Configuration of the sample sequencers is slightly more complex than the module initialization
because each sample sequencer is completely programmable.
The configuration for each sample sequencer should be as follows:
1. Ensure that the sample sequencer is disabled by clearing the corresponding ASENn bit in the
ADCACTSS register. Programming of the sample sequencers is allowed without having them
enabled. Disabling the sequencer during programming prevents erroneous execution if a trigger
event were to occur during the configuration process.
2. Configure the trigger event for the sample sequencer in the ADCEMUX register.
3. For each sample in the sample sequence, configure the corresponding input source in the
ADCSSMUXn register.
4. For each sample in the sample sequence, configure the sample control bits in the corresponding
nibble in the ADCSSCTLn register. When programming the last nibble, ensure that the END bit
is set. Failure to set the END bit causes unpredictable behavior.
5. If interrupts are to be used, set the corresponding MASK bit in the ADCIM register.
6. Enable the sample sequencer logic by setting the corresponding ASENn bit in the ADCACTSS
register.
12.5
Register Map
Table 12-4 on page 544 lists the ADC registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that ADC module's base address of:
■ ADC0: 0x4003.8000
■ ADC1: 0x4003.9000
Note that the ADC module clock must be enabled before the registers can be programmed (see
page 254). There must be a delay of 3 system clocks after the ADC module clock is enabled before
any ADC module registers are accessed.
Table 12-4. ADC Register Map
Offset Name
Type
0x000 ADCACTSS
0x004 ADCRIS
0x008 ADCIM
0x00C ADCISC
0x010 ADCOSTAT
0x014 ADCEMUX
R/W
RO
R/W
R/W1C
R/W1C
R/W
Reset
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
Description
ADC Active Sample Sequencer
ADC Raw Interrupt Status
ADC Interrupt Mask
ADC Interrupt Status and Clear
ADC Overflow Status
ADC Event Multiplexer Select
See
page
547
548
550
552
555
557
544
January 21, 2012
Texas Instruments-Production Data