LM3S5K36 Datasheet, PDF (145/1050 Pages) Texas Instruments – Stellaris® LM3S5K36 Microcontroller

Stellaris^® LM3S5K36 Microcontroller
Register 35: Configuration and Control (CFGCTRL), offset 0xD14
Note: This register can only be accessed from privileged mode.
The CFGCTRL register controls entry to Thread mode and enables: the handlers for NMI, hard fault
and faults escalated by the FAULTMASK register to ignore bus faults; trapping of divide by zero
and unaligned accesses; and access to the SWTRIG register by unprivileged software (see page 133).
Configuration and Control (CFGCTRL)
Base 0xE000.E000
Offset 0xD14
Type R/W, reset 0x0000.0200
31
30
29
28
27
Type RO
RO
RO
RO
RO
Reset
0
0
0
0
0
15
14
13
12
11
reserved
Type RO
RO
RO
RO
RO
Reset
0
0
0
0
0
26
25
24
23
22
21
reserved
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
10
9
8
7
6
5
STKALIGN BFHFNMIGN
reserved
RO
R/W
R/W
RO
RO
RO
0
1
0
0
0
0
20
19
18
17
16
RO
RO
RO
RO
RO
0
0
0
0
0
4
3
2
1
0
DIV0 UNALIGNED reserved MAINPEND BASETHR
R/W
R/W
RO
R/W
R/W
0
0
0
0
0
Bit/Field
31:10
9
8
7:5
Name
reserved
STKALIGN
BFHFNMIGN
reserved
Type
RO
R/W
R/W
RO
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
Stack Alignment on Exception Entry
Value Description
0 The stack is 4-byte aligned.
1 The stack is 8-byte aligned.
On exception entry, the processor uses bit 9 of the stacked PSR to
indicate the stack alignment. On return from the exception, it uses this
stacked bit to restore the correct stack alignment.
0
Ignore Bus Fault in NMI and Fault
This bit enables handlers with priority -1 or -2 to ignore data bus faults
caused by load and store instructions. The setting of this bit applies to
the hard fault, NMI, and FAULTMASK escalated handlers.
Value Description
0 Data bus faults caused by load and store instructions cause a
lock-up.
1 Handlers running at priority -1 and -2 ignore data bus faults
caused by load and store instructions.
Set this bit only when the handler and its data are in absolutely safe
memory. The normal use of this bit is to probe system devices and
bridges to detect control path problems and fix them.
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
January 21, 2012
145
Texas Instruments-Production Data