LM3S5K36 Datasheet, PDF (730/1050 Pages) Texas Instruments – Stellaris® LM3S5K36 Microcontroller

Inter-Integrated Circuit (I²C) Interface
Register 9: I²C Master Configuration (I2CMCR), offset 0x020
This register configures the mode (Master or Slave) and sets the interface for test mode loopback.
I2C Master Configuration (I2CMCR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x020
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
SFE
MFE
reserved
LPBK
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
RO
RO
RO
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:6
5
Name
reserved
SFE
Type
RO
R/W
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
I²C Slave Function Enable
Value Description
1 Slave mode is enabled.
0 Slave mode is disabled.
4
MFE
R/W
0
I²C Master Function Enable
Value Description
1 Master mode is enabled.
0 Master mode is disabled.
3:1
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
LPBK
R/W
0
I²C Loopback
Value Description
1 The controller in a test mode loopback configuration.
0 Normal operation.
15.7
Register Descriptions (I²C Slave)
The remainder of this section lists and describes the I²C slave registers, in numerical order by
address offset.
730
January 21, 2012
Texas Instruments-Production Data