LM3S5K36 Datasheet, PDF (639/1050 Pages) Texas Instruments – Stellaris® LM3S5K36 Microcontroller

Stellaris^® LM3S5K36 Microcontroller
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040
The UARTMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
UART Masked Interrupt Status (UARTMIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x040
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LME5MIS LME1MIS LMSBMIS
reserved
OEMIS BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:16
15
14
13
Name
reserved
LME5MIS
LME1MIS
LMSBMIS
Type
RO
RO
RO
RO
Reset
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
LIN Mode Edge 5 Masked Interrupt Status
Value Description
1 An unmasked interrupt was signaled due to the 5th falling edge
of the LIN Sync Field.
0 An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the LME5IC bit in the UARTICR
register.
LIN Mode Edge 1 Masked Interrupt Status
Value Description
1 An unmasked interrupt was signaled due to the 1st falling edge
of the LIN Sync Field.
0 An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the LME1IC bit in the UARTICR
register.
LIN Mode Sync Break Masked Interrupt Status
Value Description
1 An unmasked interrupt was signaled due to the receipt of a LIN
Sync Break.
0 An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the LMSBIC bit in the UARTICR
register.
January 21, 2012
639
Texas Instruments-Production Data