LM3S5K36 Datasheet, PDF (831/1050 Pages) Texas Instruments – Stellaris® LM3S5K36 Microcontroller

Stellaris^® LM3S5K36 Microcontroller
Register 51: USB Control and Status Endpoint 0 High (USBCSRH0), offset
0x103
USBSR0H is an 8-bit register that provides control and status bits for endpoint 0.
USB Control and Status Endpoint 0 High (USBCSRH0)
Base 0x4005.0000
Offset 0x103
Type W1C, reset 0x00
7
6
5
4
3
2
1
0
reserved
FLUSH
Type RO
RO
RO
RO
RO
RO
RO
R/W
Reset
0
0
0
0
0
0
0
0
Bit/Field
7:1
0
Name
reserved
FLUSH
Type
RO
R/W
Reset
0x00
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Flush FIFO
Value Description
0 No effect.
1 Flushes the next packet to be transmitted/read from the endpoint
0 FIFO. The FIFO pointer is reset and the TXRDY/RXRDY bit is
cleared.
This bit is automatically cleared after the flush is performed.
Important: ^{This bit should only be set when TXRDY/RXRDY is set.}
At other times, it may cause data to be corrupted.
January 21, 2012
831
Texas Instruments-Production Data