LM3S5K36 Datasheet, PDF (641/1050 Pages) Texas Instruments – Stellaris® LM3S5K36 Microcontroller

Stellaris^® LM3S5K36 Microcontroller
Bit/Field
5
4
3:0
Name
TXMIS
RXMIS
reserved
Type
RO
RO
RO
Reset
0
0
0
Description
UART Transmit Masked Interrupt Status
Value Description
1 An unmasked interrupt was signaled due to passing through
the specified transmit FIFO level (if the EOT bit is clear) or due
to the transmission of the last data bit (if the EOT bit is set).
0 An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register
or by writing data to the transmit FIFO until it becomes greater than the
trigger level, if the FIFO is enabled, or by writing a single byte if the FIFO
is disabled.
UART Receive Masked Interrupt Status
Value Description
1 An unmasked interrupt was signaled due to passing through
the specified receive FIFO level.
0 An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register
or by reading data from the receive FIFO until it becomes less than the
trigger level, if the FIFO is enabled, or by reading a single byte if the
FIFO is disabled.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
January 21, 2012
641
Texas Instruments-Production Data