LM3S5K36 Datasheet, PDF (842/1050 Pages) Texas Instruments – Stellaris® LM3S5K36 Microcontroller

Universal Serial Bus (USB) Controller
Bit/Field
7
6
5
4
3
Name
CLRDT
STALLED
STALL
FLUSH
DATAERR
Type
W1C
R/W
R/W
R/W
RO
Reset
0
0
0
0
Description
Clear Data Toggle
Writing a 1 to this bit clears the DT bit in the USBRXCSRHn register.
Endpoint Stalled
Value Description
0 A STALL handshake has not been transmitted.
1 A STALL handshake has been transmitted.
Software must clear this bit.
Send STALL
Value Description
0 No effect.
1 Issues a STALL handshake.
Software must clear this bit to terminate the STALL condition.
Note: This bit has no effect where the endpoint is being used for
isochronous transfers.
Flush FIFO
Value Description
0 No effect.
1 Flushes the next packet from the endpoint receive FIFO. The
FIFO pointer is reset and the RXRDY bit is cleared.
The CPU writes a 1 to this bit to flush the next packet to be read from
the endpoint receive FIFO. The FIFO pointer is reset and the RXRDY bit
is cleared. Note that if the FIFO is double-buffered, FLUSH may have
to be set twice to completely clear the FIFO.
Important: ^{This bit should only be set when the RXRDY bit is set. At}
other times, it may cause data to be corrupted.
0
Data Error
Value Description
0 Normal operation.
1 Indicates that RXRDY is set and the data packet has a CRC or
bit-stuff error.
This bit is cleared when RXRDY is cleared.
Note: This bit is only valid when the endpoint is operating in
Isochronous mode. In Bulk mode, it always returns zero.
842
January 21, 2012
Texas Instruments-Production Data