LM3S5K36 Datasheet, PDF (277/1050 Pages) Texas Instruments – Stellaris® LM3S5K36 Microcontroller

Stellaris^® LM3S5K36 Microcontroller
Register 36: Software Reset Control 0 (SRCR0), offset 0x040
This register allows individual modules to be reset. Writes to this register are masked by the bits in
the Device Capabilities 1 (DC1) register.
Software Reset Control 0 (SRCR0)
Base 0x400F.E000
Offset 0x040
Type R/W, reset 0x00000000
31
30
29
28
27
26
25
reserved
WDT1
reserved
Type RO
RO
RO
R/W
RO
RO
RO
Reset
0
0
0
0
0
0
0
15
14
13
12
11
10
9
reserved
Type RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
24
CAN0
R/W
0
8
RO
0
23
22
21
reserved
RO
RO
RO
0
0
0
20
PWM
R/W
0
19
18
reserved
RO
RO
0
0
17
ADC1
R/W
0
16
ADC0
R/W
0
7
6
5
4
3
2
1
0
HIB
reserved
WDT0
reserved
RO
R/W
RO
RO
R/W
RO
RO
RO
0
0
0
0
0
0
0
0
Bit/Field
31:29
28
27:25
24
23:21
20
19:18
17
Name
reserved
WDT1
reserved
CAN0
reserved
PWM
reserved
ADC1
Type
RO
R/W
RO
R/W
RO
R/W
RO
R/W
Reset
0
0
0
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
WDT1 Reset Control
When this bit is set, Watchdog Timer module 1 is reset. All internal data
is lost and the registers are returned to their reset states. This bit must
be manually cleared after being set.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
CAN0 Reset Control
When this bit is set, CAN module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM Reset Control
When this bit is set, PWM module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ADC1 Reset Control
When this bit is set, ADC module 1 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
January 21, 2012
277
Texas Instruments-Production Data