LM3S5K36 Datasheet, PDF (193/1050 Pages) Texas Instruments – Stellaris® LM3S5K36 Microcontroller

Stellaris^® LM3S5K36 Microcontroller
■ Crystal input selection
Important: Write the RCC register prior to writing the RCC2 register. If a subsequent write to the
RCC register is required, include another register access after writing the RCC register
and before writing the RCC2 register.
Figure 5-5 shows the logic for the main clock tree. The peripheral blocks are driven by the system
clock signal and can be individually enabled/disabled. When the PLL is enabled, the ADC clock
signal is automatically divided down to 16 MHz from the PLL output for proper ADC operation. The
PWM clock signal is a synchronous divide of the system clock to provide the PWM circuit with more
range (set with PWMDIV in RCC).
Note: When the ADC module is in operation, the system clock must be at least 16 MHz. When
the USB module is in operation, MOSC must be the clock source, either with or without
using the PLL, and the system clock must be at least 30 MHz.
January 21, 2012
193
Texas Instruments-Production Data