LM3S5K36 Datasheet, PDF (37/1050 Pages) Texas Instruments – Stellaris® LM3S5K36 Microcontroller

Stellaris^® LM3S5K36 Microcontroller
Table 1. Revision History (continued)
Date
June 2010
Revision Description
7299 ■ Removed 4.194304-MHz crystal as a source for the system clock and PLL.
■ Summarized ROM contents descriptions in the "Internal Memory" chapter and removed various
ROM appendices.
■ Clarified DMA channel terminology: changed name of DMA Channel Alternate Select (DMACHALT)
register to DMA Channel Assignment (DMACHASGN) register, changed CHALT bit field to CHASGN,
and changed terminology from primary and alternate channels to primary and secondary channels.
■ Changed bits 3:0 to reserved in UARTIM, UARTRIS, UARTMIS, and UARTICR registers. These
bits are only used in devices with the UART Modem Status feature.
■ In Signal Tables chapter, added table "Connections for Unused Signals."
■ In "Electrical Characteristics" chapter:
– In "Reset Characteristics" table, corrected Supply voltage (VDD) rise time.
– Clarified figure "SDRAM Initialization and Load Mode Register Timing".
May 2010
7164
■ Added data sheets for five new Stellaris® Tempest-class parts: LM3S1R26, LM3S1621, LM3S1B21,
LM3S9781, and LM3S9B81.
■ Additional minor data sheet clarifications and corrections.
May 2010
7101
■ Added pin table "Possible Pin Assignments for Alternate Functions", which lists the signals based
on number of possible pin assignments. This table can be used to plan how to configure the pins
for a particular functionality.
■ Additional minor data sheet clarifications and corrections.
March 2010
6983
■ Extended TBRL bit field in GPTMTBR register.
■ Added DISCON bit to Device Mode table for USBIE register
■ Removed extraneous 100-pin tables from the chapters.
■ Additional minor data sheet clarifications and corrections.
March 2010
6912
■ Corrected the pin tables in the Signal Description sections within chapters (tables were correct in
Signal Tables chapter but incorrect within chapters).
■ Renamed the USER_DBG register to the BOOTCFG register in the Internal Memory chapter. Added
information on how to use a GPIO pin to force the ROM Boot Loader to execute on reset.
■ Added three figures to the ADC chapter on sample phase control.
■ Clarified configuration of USB0VBUS and USB0ID in OTG mode.
■ Corrected the pin name for the VDDC signals, which were mistakenly labelled as VDD25.
January 21, 2012
37
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