LM3S5K36 Datasheet, PDF (5/1050 Pages) Texas Instruments – Stellaris® LM3S5K36 Microcontroller

Stellaris^® LM3S5K36 Microcontroller
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Hibernation Module .............................................................................................. 283
6.1 Block Diagram ............................................................................................................ 284
6.2 Signal Description ....................................................................................................... 284
6.3 Functional Description ................................................................................................. 285
6.3.1 Register Access Timing ............................................................................................... 285
6.3.2 Hibernation Clock Source ............................................................................................ 285
6.3.3 System Implementation ............................................................................................... 287
6.3.4 Battery Management ................................................................................................... 287
6.3.5 Real-Time Clock .......................................................................................................... 288
6.3.6 Battery-Backed Memory .............................................................................................. 288
6.3.7 Power Control Using HIB ............................................................................................. 288
6.3.8 Power Control Using VDD3ON Mode ........................................................................... 289
6.3.9 Initiating Hibernate ...................................................................................................... 289
6.3.10 Waking from Hibernate ................................................................................................ 289
6.3.11 Interrupts and Status ................................................................................................... 289
6.4 Initialization and Configuration ..................................................................................... 290
6.4.1 Initialization ................................................................................................................. 290
6.4.2 RTC Match Functionality (No Hibernation) .................................................................... 291
6.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 291
6.4.4 External Wake-Up from Hibernation .............................................................................. 291
6.4.5 RTC or External Wake-Up from Hibernation .................................................................. 291
6.5 Register Map .............................................................................................................. 292
6.6 Register Descriptions .................................................................................................. 292
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7.1
7.2
7.2.1
7.2.2
7.2.3
7.3
7.4
7.5
Internal Memory ................................................................................................... 309
Block Diagram ............................................................................................................ 309
Functional Description ................................................................................................. 309
SRAM ........................................................................................................................ 310
ROM .......................................................................................................................... 310
Flash Memory ............................................................................................................. 312
Register Map .............................................................................................................. 317
Flash Memory Register Descriptions (Flash Control Offset) ............................................ 318
Memory Register Descriptions (System Control Offset) .................................................. 330
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Micro Direct Memory Access (μDMA) ................................................................ 346
8.1 Block Diagram ............................................................................................................ 347
8.2 Functional Description ................................................................................................. 347
8.2.1 Channel Assignments .................................................................................................. 348
8.2.2 Priority ........................................................................................................................ 349
8.2.3 Arbitration Size ............................................................................................................ 349
8.2.4 Request Types ............................................................................................................ 349
8.2.5 Channel Configuration ................................................................................................. 350
8.2.6 Transfer Modes ........................................................................................................... 352
8.2.7 Transfer Size and Increment ........................................................................................ 360
8.2.8 Peripheral Interface ..................................................................................................... 360
8.2.9 Software Request ........................................................................................................ 360
8.2.10 Interrupts and Errors .................................................................................................... 361
8.3 Initialization and Configuration ..................................................................................... 361
8.3.1 Module Initialization ..................................................................................................... 361
8.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 361
January 21, 2012
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