LM3S5K36 Datasheet, PDF (719/1050 Pages) Texas Instruments – Stellaris® LM3S5K36 Microcontroller

Stellaris^® LM3S5K36 Microcontroller
Register 2: I²C Master Control/Status (I2CMCS), offset 0x004
This register accesses status bits when read and control bits when written. When read, the status
register indicates the state of the I²C bus controller. When written, the control register configures
the I²C controller operation.
The START bit generates the START or REPEATED START condition. The STOP bit determines if
the cycle stops at the end of the data cycle or continues on to a repeated START condition. To
generate a single transmit cycle, the I²C Master Slave Address (I2CMSA) register is written with
the desired address, the R/S bit is cleared, and this register is written with ACK=X (0 or 1), STOP=1,
START=1, and RUN=1 to perform the operation and stop. When the operation is completed (or
aborted due an error), an interrupt becomes active and the data may be read from the I2CMDR
register. When the I²C module operates in Master receiver mode, the ACK bit is normally set, causing
the I²C bus controller to transmit an acknowledge automatically after each byte. This bit must be
cleared when the I²C bus controller requires no further data to be transmitted from the slave
transmitter.
Read-Only Status Register
I2C Master Control/Status (I2CMCS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x004
Type RO, reset 0x0000.0020
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
BUSBSY IDLE ARBLST DATACK ADRACK ERROR BUSY
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Bit/Field
31:7
6
5
Name
reserved
BUSBSY
IDLE
Type
RO
RO
RO
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
Bus Busy
Value Description
0
The I²C bus is idle.
1
The I²C bus is busy.
The bit changes based on the START and STOP conditions.
1
I²C Idle
Value Description
0
The I²C controller is not idle.
1
The I²C controller is idle.
January 21, 2012
719
Texas Instruments-Production Data