MSP430F673X Datasheet, PDF (81/121 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

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MSP430F673x
MSP430F672x
SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN TYP
DV_{CC(PGM/ERASE)} Program and erase supply voltage
I_PGM
Average supply current from DV_CC during program
I_ERASE
Average supply current from DV_CC during erase
I_MERASE, I_BANK
t_CPT
Average supply current from DV_CC during mass erase or bank erase
Cumulative program time
See ⁽¹⁾
Program/erase endurance
1.8
3
10⁴
10⁵
t_Retention
t_Word
t_{Block, 0}
Data retention duration
Word or byte program time
Block program time for first byte or word
T_J = 25°C
100
See ⁽²⁾
64
See ⁽²⁾
49
t_{Block, 1–(N–1)}
Block program time for each additional byte or word, except for last
byte or word
See ⁽²⁾
37
t_{Block, N}
Block program time for last byte or word
See ⁽²⁾
55
t_Erase
Erase time for segment erase, mass erase, and bank erase when
available
See ⁽²⁾
23
f_MCLK,MGR
MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)
0
MAX UNIT
3.6 V
5 mA
8 mA
5 mA
16 ms
cycles
years
85 µs
65 µs
49 µs
73 µs
32 ms
1 MHz
(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word- or byte-write and block-write modes.
(2) These values are hardwired into the flash controller's state machine.
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN TYP
f_SBW
t_SBW,Low
t_{SBW, En}
Spy-Bi-Wire input frequency
Spy-Bi-Wire low clock pulse length
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
edge) ⁽¹⁾
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
0
0.025
t_SBW,Rst
f_TCK
Spy-Bi-Wire return to normal operation time
TCK input frequency for 4-wire JTAG⁽²⁾
15
2.2 V
0
3V
0
R_internal
Internal pulldown resistance on TEST
2.2 V, 3 V
45
60
MAX UNIT
20 MHz
15 µs
1 µs
100 µs
5
MHz
10
80 kΩ
(1) Tools accessing the Spy-Bi-Wire interface need to wait for the minimum t_SBW,En time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
(2) f_TCK may be restricted to meet the timing requirements of the module selected.
Copyright © 2011–2012, Texas Instruments Incorporated
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