MSP430F673X Datasheet, PDF (67/121 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

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MSP430F673x
MSP430F672x
SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾
PARAMETER
t_STE,LEAD STE lead time, STE active to clock
TEST CONDITIONS
V_CC
2.0 V
3.0 V
MIN TYP
4
3
t_STE,LAG STE lag time, Last clock to STE inactive
2.0 V
0
3.0 V
0
t_STE,ACC STE access time, STE active to SOMI data out
2.0 V
3.0 V
t_STE,DIS
STE disable time, STE inactive to SOMI high
impedance
2.0 V
3.0 V
t_SU,SI
SIMO input data setup time
2.0 V
2
3.0 V
1
t_HD,SI
SIMO input data hold time
2.0 V
2
3.0 V
2
t_VALID,SO SOMI output data valid time⁽²⁾
UCLK edge to SOMI valid,
C_L = 20 pF
2.0 V
3.0 V
t_HD,SO
SOMI output data hold time⁽³⁾
C_L = 20 pF
2.0 V
24
3.0 V
16
MAX UNIT
ns
ns
46
ns
24
38
ns
25
ns
ns
55
ns
32
ns
(1) f_UCxCLK = 1/2t_LO/HI with tL_O/HI = max(t_{VALID,MO(Master)} + t_SU,SI(eUSCI), t_{SU,MI(Master)} + t_{VALID,SO(eUSCI)}).
For the master's parameters t_{SU,MI(Master)} and t_{VALID,MO(Master)} refer to the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 15 and Figure 16.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams
inFigure 15 and Figure 16.
UCMODEx = 01
STE
UCMODEx = 10
CKPL = 0
UCLK
CKPL = 1
SIMO
t_STE,LEAD
1/f_UCxCLK
t_LOW/HIGH
t_LOW/HIGH
t_STE,LAG
t_SU,SIMO
t_HD,SIMO
SOMI
t_ACC
t_VALID,SOMI
t_DIS
Figure 15. SPI Slave Mode, CKPH = 0
Copyright © 2011–2012, Texas Instruments Incorporated
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