MSP430F673X Datasheet, PDF (65/121 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

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MSP430F673x
MSP430F672x
SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
eUSCI (SPI Master Mode) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾
t_HD,MI
PARAMETER
SOMI input data hold
time
TEST CONDITIONS
V_CC
2.0 V
3.0 V
MIN TYP
0
0
t_VALID,MO
SIMO output data valid
time ⁽²⁾
UCLK edge to SIMO valid, C_L = 20 pF
2.0 V
3.0 V
t_HD,MO
SIMO output data hold
time ⁽³⁾
C_L = 20 pF
2.0 V
0
3.0 V
0
MAX UNIT
ns
9
ns
5
ns
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 15 and Figure 16.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in
Figure 15 and Figure 16.
UCMODEx = 01
STE
UCMODEx = 10
UCLK
CKPL = 0
CKPL = 1
SOMI
t_STE,LEAD
1/f_UCxCLK
t_LOW/HIGH
t_LOW/HIGH
t_STE,LAG
t_SU,MI
t_HD,MI
SIMO
t_STE,ACC
t_VALID,MO
Figure 13. SPI Master Mode, CKPH = 0
t_STE,DIS
Copyright © 2011–2012, Texas Instruments Incorporated
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