MSP430F673X Datasheet, PDF (4/121 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430F673x
MSP430F672x
SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
Functional Block Diagram, MSP430F673xIPZ, MSP430F672xIPZ
XIN XOUT
(32kHz)
DVCC DVSS AVCC AVSS AUX1 AUX2 AUX3 RST/NMI
PA
P1.x P2.x
PB
P3.x P4.x
PC
PD
P5.x P6.x P7.x P8.x
PE
P9.x
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Unified
Clock
System
ACLK
SMCLK
MCLK
128kB
96KB
64KB
32KB
16KB
Flash
CPUXV2
and
Working
Registers
(25MHz)
8kB
4KB
2KB
1KB
RAM
SYS
Watchdog
Port
Mapping
Controller
CRC16
MPY32
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
PA
1×16 I/Os
I/O Ports
P3/P4
2×8 I/Os
PB
1×16 I/Os
I/O Ports
P5/P6
2×8 I/Os
PC
1×16 I/Os
I/O Ports
P7/P8
2×8 I/Os
PD
1×16 I/Os
I/O Ports
P9
1×4 I/O
PE
1×4 I/O
PJ.x
EEM
(S: 3+1)
JTAG/
SBW
Interface/
Port PJ
PMM
Auxiliary
Supplies
LDO
SVM/SVS
BOR
SD24_B
3 Channel
2 Channel
ADC10_A
LCD_C
REF
10 Bit
200 KSPS
8MUX
Up to 320
Segments
Reference
1.5V, 2.0V,
2.5V
RTC_C
TA0
Timer_A
3 CC
Registers
TA1
TA2
TA3
Timer_A
2 CC
Registers
eUSCI_A0
eUSCI_A1
eUSCI_A2
(UART,
IrDA,SPI)
eUSCI_B0
(SPI, I2C)
DMA
3 Channel
Functional Block Diagram, MSP430F673xIPN, MSP430F672xIPN
XIN XOUT
(32kHz)
DVCC DVSS AVCC AVSS AUX1 AUX2 AUX3 RST/NMI
PA
P1.x P2.x
PB
P3.x P4.x
PC
P5.x P6.x
Unified
Clock
System
ACLK
SMCLK
MCLK
128KB
96KB
64KB
32KB
16KB
Flash
8KB
4KB
2KB
1KB
RAM
DMA
3 Channel
SYS
Watchdog
Port
Mapping
Controller
CRC16
MPY32
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
PA
1×16 I/Os
I/O Ports
P3/P4
2×8 I/Os
PB
1×16 I/Os
I/O Ports
P5/P6
2×8 I/Os
PC
1×16 I/Os
CPUXV2
and
Working
Registers
(25MHz)
PJ.x
EEM
(S: 3+1)
JTAG/
SBW
Interface/
Port PJ
PMM
Auxiliary
Supplies
LDO
SVM/SVS
BOR
SD24_B
3 Channel
2 Channel
ADC10_A
LCD_C
REF
10 Bit
200 KSPS
8MUX
Up to 320
Segments
Reference
1.5V, 2.0V,
2.5V
RTC_C
TA0
Timer_A
3 CC
Registers
TA1
TA2
TA3
Timer_A
2 CC
Registers
eUSCI_A0
eUSCI_A1
eUSCI_A2
(UART,
IrDA,SPI)
eUSCI_B0
(SPI, I2C)
4
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