MSP430F673X Datasheet, PDF (13/121 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

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MSP430F673x
MSP430F672x
SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
TERMINAL
NAME
P7.2/S9
P7.3/S8
P7.4/S7
P7.5/S6
P7.6/S5
P7.7/S4
P8.0/S3
P8.1/S2
P8.2/S1
P8.3/S0
TEST/SBWTCK
PJ.0/SMCLK/TDO
PJ.1/MCLK/TDI/TCLK
PJ.2/ADC10CLK/TMS
PJ.3/ACLK/TCK
RST/NMI/SBWTDIO
Table 5. Terminal Functions, MSP430F67xxIPZ (continued)
NO. I/O⁽¹⁾
PZ
DESCRIPTION
85 I/O ^{General-purpose digital I/O}
LCD segment output S9
86 I/O ^{General-purpose digital I/O}
LCD segment output S8
87 I/O ^{General-purpose digital I/O}
LCD segment output S7
88 I/O ^{General-purpose digital I/O}
LCD segment output S6
89 I/O ^{General-purpose digital I/O}
LCD segment output S5
90 I/O ^{General-purpose digital I/O}
LCD segment output S4
91 I/O ^{General-purpose digital I/O}
LCD segment output S3
92 I/O ^{General-purpose digital I/O}
LCD segment output S2
93 I/O ^{General-purpose digital I/O}
LCD segment output S1
94 I/O ^{General-purpose digital I/O}
LCD segment output S0
95
I ^{Test mode pin – select digital I/O on JTAG pins}
Spy-Bi-Wire input clock
General-purpose digital I/O
96 I/O _{SMCLK clock output}
Test data output
General-purpose digital I/O
97 I/O _{MCLK clock output}
Test data input or Test clock input
General-purpose digital I/O
98 I/O _{ADC10_A clock output}
Test mode select
General-purpose digital I/O
99 I/O _{ACLK clock output}
Test clock
Reset input active low
100 I/O _{Non-maskable interrupt input}
Spy-Bi-Wire data input/output
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