MSP430F673X Datasheet, PDF (7/121 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

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Pin Designation, MSP430F673xIPN
MSP430F673x
MSP430F672x
SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
SD0P0
SD0N0
SD1P0
SD1N0
SD2P0
SD2N0
VREF
AVSS
AVCC
VASYS
P1.0/PM_TA0.0/VeREF-/A2
P1.1/PM_TA0.1/VeREF+/A1
P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0
P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03
AUXVCC2
AUXVCC1
VDSYS
DVCC
DVSS
VCORE
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
2
59
3
58
4
57
5
56
6
55
7
54
8
53
9
52
10
51
PN PACKAGE
11
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
DVSS
DVSYS
P5.1/S14
P5.0/S15
P4.7/S16
P4.6/S17
P4.5/S18
P4.4/S19
P4.3/S20
P4.2/S21
P4.1/S22
P4.0/S23
P3.7/PM_SD2DIO/S24
P3.6/PM_SD1DIO/S25
P3.5/PM_SD0DIO/S26
P3.4/PM_SDCLK/S27
P3.3/PM_TA0.2/S28
P3.2/PM_TACLK/PM_RTCCLK/S29
P3.1/PM_TA2.1/S30/BSL_RX
P3.0/PM_TA2.0/S31/BSL_TX
NOTE: The secondary digital functions on Ports P1, P2, and P3 are fully mappable. The pin designation shows the default
mapping. See Table 14 for details.
NOTE: The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
CAUTION: The LCDCAP/R33 pin must be connected to DVSS if not used.
Copyright © 2011–2012, Texas Instruments Incorporated
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