MSP430F673X Datasheet, PDF (17/121 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

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MSP430F673x
MSP430F672x
SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
TERMINAL
NAME
P5.0/S15
P5.1/S14
DVSYS ⁽⁵⁾
DVSS
P5.2/S13
P5.3/S12
P5.4/S11
P5.5/S10
P5.6/S9
P5.7/S8
P6.0/S7
P6.1/S6
P6.2/S5
P6.3/S4
P6.4/S3
P6.5/S2
P6.6/S1
P6.7/S0
TEST/SBWTCK
PJ.0/SMCLK/TDO
PJ.1/MCLK/TDI/TCLK
Table 6. Terminal Functions, MSP430F67xxIPN (continued)
NO. I/O⁽¹⁾
PN
DESCRIPTION
57 I/O ^{General-purpose digital I/O}
LCD segment output S15
58 I/O ^{General-purpose digital I/O}
LCD segment output S14
59
Digital power supply for I/Os
60
Digital ground supply
61 I/O ^{General-purpose digital I/O}
LCD segment output S13
62 I/O ^{General-purpose digital I/O}
LCD segment output S12
63 I/O ^{General-purpose digital I/O}
LCD segment output S11
64 I/O ^{General-purpose digital I/O}
LCD segment output S10
65 I/O ^{General-purpose digital I/O}
LCD segment output S9
66 I/O ^{General-purpose digital I/O}
LCD segment output S8
67 I/O ^{General-purpose digital I/O}
LCD segment output S7
68 I/O ^{General-purpose digital I/O}
LCD segment output S6
69 I/O ^{General-purpose digital I/O}
LCD segment output S5
70 I/O ^{General-purpose digital I/O}
LCD segment output S4
71 I/O ^{General-purpose digital I/O}
LCD segment output S3
72 I/O ^{General-purpose digital I/O}
LCD segment output S2
73 I/O ^{General-purpose digital I/O}
LCD segment output S1
74 I/O ^{General-purpose digital I/O}
LCD segment output S0
75
I ^{Test mode pin – select digital I/O on JTAG pins}
Spy-Bi-Wire input clock
General-purpose digital I/O
76 I/O _{SMCLK clock output}
Test data output
General-purpose digital I/O
77 I/O _{MCLK clock output}
Test data input or Test clock input
(5) The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
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