MSP430F673X Datasheet, PDF (47/121 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

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MSP430F673x
MSP430F672x
SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
Absolute Maximum Ratings⁽¹⁾
over operating free-air temperature range (unless otherwise noted)
Voltage applied at DVCC to DVSS
Voltage applied to any pin (excluding VCORE)⁽²⁾
Diode current at any device pin
Storage temperature range, T_stg ⁽³⁾
Maximum junction temperature, T_J
-0.3 V to 4.1 V
-0.3 V to V_CC + 0.3 V
±2 mA
–55°C to 150°C
95°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to V_SS. V_CORE is for internal device usage only. No external DC loading or voltage should be applied.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Recommended Operating Conditions
MIN NOM MAX UNIT
PMMCOREVx = 0
1.8
3.6 V
V_CC
Supply voltage during program execution and flash
programming. V(AVCC) = V(DVCC) = V_CC ⁽¹⁾
PMMCOREVx = 0, 1
PMMCOREVx = 0, 1, 2
2.0
2.2
3.6 V
3.6 V
PMMCOREVx = 0, 1, 2, 3
2.4
3.6 V
V_SS
T_A
T_J
C_VCORE
C_DVCC/
C_VCORE
Supply voltage V(AVSS) = V(DVSS) = V_SS
Operating free-air temperature
Operating junction temperature
Recommended capacitor at VCORE
Capacitor ratio of DVCC to VCORE
I version
I version
PMMCOREVx = 0,
1.8 V ≤ V_CC ≤ 3.6 V
(default condition)
0
–40
–40
470
10
V
85 °C
85 °C
nF
0
8.0
f_SYSTEM
I_LOAD,
DVCCD
I_LOAD,
AUX1D
I_LOAD,
AUX2D
I_LOAD,
AVCCA
I_LOAD,
AUX1A
I_LOAD,
AUX2A
Processor frequency (maximum MCLK frequency)⁽²⁾⁽³⁾
(see Figure 1)
Maximum load current that can be drawn from DVCC for
core and IO (I_LOAD = I_CORE + I_IO)
Maximum load current that can be drawn from AUXVCC1 for
core and IO (I_LOAD = I_CORE + I_IO)
Maximum load current that can be drawn from AUXVCC2 for
core and IO (I_LOAD = I_CORE + I_IO)
Maximum load current that can be drawn from AVCC for
analog modules (I_LOAD = I_Modules)
Maximum load current that can be drawn from AUXVCC1 for
analog modules (I_LOAD = I_Modules)
Maximum load current that can be drawn from AUXVCC2 for
analog modules (I_LOAD = I_Modules)
PMMCOREVx = 1,
2.0 V ≤ V_CC ≤ 3.6 V
PMMCOREVx = 2,
2.2 V ≤ V_CC ≤ 3.6 V
PMMCOREVx = 3,
2.4 V ≤ V_CC ≤ 3.6 V
0
12.0
MHz
0
20.0
0
25.0
20 mA
20 mA
20 mA
10 mA
5 mA
5 mA
(1) It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between V(AVCC) and V(DVCC)
can be tolerated during power up and operation.
(2) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
(3) Modules may have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet.
Copyright © 2011–2012, Texas Instruments Incorporated
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