MSP430F673X Datasheet, PDF (64/121 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430F673x
MSP430F672x
SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Internal: SMCLK, ACLK
f_TA
Timer_A input clock frequency
External: TACLK
Duty cycle = 50% ± 10%
V_CC
1.8 V/
3.0 V
MIN TYP
t_TA,cap
Timer_A capture timing
All capture inputs.
Minimum pulse width required for
capture.
1.8 V/
3.0 V
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MAX UNIT
25 MHz
ns
eUSCI (UART Mode) - Recommended Operating Conditions
PARAMETER
CONDITIONS
f_eUSCI
eUSCI input clock frequency
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
f_BITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
V_CC
MIN TYP MAX UNIT
f_SYSTEM MHz
5 MHz
eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UCGLITx = 0
V_CC
MIN TYP
10
15
t_t
UART receive deglitch time⁽¹⁾
UCGLITx = 1
UCGLITx = 2
2.0 V/3.0
V
30
50
50
80
UCGLITx = 3
70 120
MAX
25
85
150
200
UNIT
ns
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
eUSCI (SPI Master Mode) - Recommended Operating Conditions
PARAMETER
CONDITIONS
V_CC
f_eUSCI
eUSCI input clock frequency
Internal: SMCLK, ACLK
Duty cycle = 50% ± 10%
MIN TYP MAX UNIT
f_SYSTEM MHz
eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾
t_STE,LEAD
PARAMETER
STE lead time, STE
active to clock
TEST CONDITIONS
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
V_CC
2.0 V/3.0 V
2.0 V/3.0 V
MIN TYP
150
150
t_STE,LAG
STE lag time, Last clock ^{UCSTEM = 0, UCMODEx = 01 or 10}
to STE inactive
UCSTEM = 1, UCMODEx = 01 or 10
2.0 V/3.0 V
200
2.0 V/3.0 V
200
t_STE,ACC
STE access time, STE
active to SIMO data out
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
2.0 V
3.0 V
2.0 V
3.0 V
t_STE,DIS
STE disable time, STE
inactive to SIMO high
impedance
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
2.0 V
3.0 V
2.0 V
3.0 V
t_SU,MI
SOMI input data setup
time
2.0 V
50
3.0 V
30
MAX UNIT
ns
ns
50
30
ns
50
30
40
25
ns
40
25
ns
(1) f_UCxCLK = 1/2t_LO/HI with tL_O/HI = max(t_{VALID,MO(eUSCI)} + t_SU,SI(Slave), t_SU,MI(eUSCI) + t_{VALID,SO(Slave)}).
For the slave's parameters t_SU,SI(Slave) and t_{VALID,SO(Slave)} refer to the SPI parameters of the attached slave.
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