MSP430F673X Datasheet, PDF (79/121 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

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MSP430F673x
MSP430F672x
SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
10-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
E_I
Integral
linearity error
E_D
Differential
linearity error
E_O
Offset error
E_G
Gain error
E_T
Total unadjusted
error
TEST CONDITIONS
1.4 V ≤ (V_eREF+ – V_eREF–)min ≤ 1.6 V
1.6 V < (V_eREF+ – V_eREF–)min ≤ V_AVCC
(V_eREF+ – V_eREF–)min ≤ (V_eREF+ – V_eREF–),
C_VeREF+ = 20 pF
(V_eREF+ – V_eREF–)min ≤ (V_eREF+ – V_eREF–),
Internal impedance of source R_S < 100 Ω, C_VREF+ = 20 pF
(V_eREF+ – V_eREF–)min ≤ (V_eREF+ – V_eREF–),
C_VeREF+ = 20 pF
(V_eREF+ – V_eREF–)min ≤ (V_eREF+ – V_eREF–),
C_VeREF+ = 20 pF
V_CC
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
MIN TYP
±1.0
MAX
±1.0
±1.0
UNIT
LSB
±1.0 LSB
±1.0 LSB
±1.0 LSB
±2.0 LSB
10-Bit ADC, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾
V_eREF+
PARAMETER
Positive external
reference voltage input
TEST CONDITIONS
V_eREF+ > V_eREF– ⁽²⁾
V_CC
MIN TYP
1.4
V_eREF–
Negative external
reference voltage input
V_eREF+ > V_eREF– ⁽³⁾
0
(V_eREF+ –
V_eREF–)
I_VeREF+
I_VeREF–
Differential external
reference voltage input
Static input current
V_eREF+ > V_eREF– ⁽⁴⁾
1.4 V ≤ V_eREF+ ≤ V_AVCC , V_eREF– = 0 V,
f_ADC10CLK = 5 MHz, ADC10SHTx = 0x0001,
Conversion rate 200 ksps
1.4 V ≤ V_eREF+ ≤ V_AVCC , V_eREF– = 0 V,
f_ADC10CLK = 5 MHz, ADC10SHTX = 0x1000,
Conversion rate 20 ksps
1.4
2.2 V, 3 V
±8.5
2.2 V, 3 V
C_VeREF+/-
Capacitance at
VeREF+/- terminal
See ⁽⁵⁾
10
MAX UNIT
AV_CC V
1.2 V
AV_CC V
±26 µA
±1 µA
µF
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, C_I, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VeREF to decouple the dynamic current required for an external
reference source if it is used for the ADC10_A. Also see the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).
Copyright © 2011–2012, Texas Instruments Incorporated
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