MSP430F673X Datasheet, PDF (27/121 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

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MSP430F673x
MSP430F672x
SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
Port Mapping Controller
The port mapping controller allows flexible and reconfigurable mapping of digital functions to P1, P2, and P3.
Table 14. Port Mapping, Mnemonics and Functions
VALUE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31(0FFh) ⁽¹⁾
PxMAPy MNEMONIC
PM_NONE
PM_UCA0RXD
PM_UCA0SOMI
PM_UCA0TXD
PM_UCA0SIMO
PM_UCA0CLK
PM_UCA0STE
PM_UCA1RXD
PM_UCA1SOMI
PM_UCA1TXD
PM_UCA1SIMO
PM_UCA1CLK
PM_UCA1STE
PM_UCA2RXD
PM_UCA2SOMI
PM_UCA2TXD
PM_ UCA2SIMO
PM_UCA2CLK
PM_UCA2STE
PM_UCB0SIMO
PM_UCB0SDA
PM_UCB0SOMI
PM_UCB0SCL
PM_UCB0CLK
PM_UCB0STE
PM_TA0.0
PM_TA0.1
PM_TA0.2
PM_TA1.0
PM_TA1.1
PM_TA2.0
PM_TA2.1
PM_TA3.0
PM_TA3.1
PM_TACLK
PM_RTCCLK
PM_SDCLK
PM_SD0DIO
PM_SD1DIO
PM_SD2DIO
PM_ANALOG
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
None
DVSS
eUSCI_A0 UART RXD (direction controlled by eUSCI – Input)
eUSCI_A0 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A0 UART TXD (direction controlled by eUSCI – Output)
eUSCI_A0 SPI slave in master out (direction controlled by eUSCI)
eUSCI_A0 clock input/output (direction controlled by eUSCI)
eUSCI_A0 SPI slave transmit enable (direction controlled by eUSCI)
eUSCI_A1 UART RXD (direction controlled by eUSCI – Input)
eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A1 UART TXD (direction controlled by eUSCI – Output)
eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)
eUSCI_A1 clock input/output (direction controlled by eUSCI)
eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI)
eUSCI_A2 UART RXD (direction controlled by eUSCI – Input)
eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A2 UART TXD (direction controlled by eUSCI – Output)
eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)
eUSCI_A2 clock input/output (direction controlled by eUSCI)
eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI)
eUSCI_B0 SPI slave in master out (direction controlled by eUSCI)
eUSCI_B0 I2C data (open drain and direction controlled by eUSCI)
eUSCI_B0 SPI slave out master in (direction controlled by eUSCI)
eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI)
eUSCI_B0 clock input/output (direction controlled by eUSCI)
eUSCI_B0 SPI slave transmit enable (direction controlled by eUSCI)
TA0 CCR0 capture input CCI0A
TA0 CCR0 compare output Out0
TA0 CCR1 capture input CCI1A
TA0 CCR1 compare output Out1
TA0 CCR2 capture input CCI2A
TA0 CCR2 compare output Out2
TA1 CCR0 capture input CCI0A
TA1 CCR0 compare output Out0
TA1 CCR1 capture input CCI1A
TA1 CCR1 compare output Out1
TA2 CCR0 capture input CCI0A
TA2 CCR0 compare output Out0
TA2 CCR1 capture input CCI1A
TA2 CCR1 compare output Out1
TA3 CCR0 capture input CCI0A
TA3 CCR0 compare output Out0
TA3 CCR1 capture input CCI1A
TA3 CCR1 compare output Out1
Timer_A clock input to
TA0, TA1, TA2, TA3
None
None
RTC_C clock output
SD24_B bit stream clock input/output (direction controlled by SD24_B)
SD24_B converter-0 bit stream data input/output (direction controlled by SD24_B)
SD24_B converter-1 bit stream data input/output (direction controlled by SD24_B)
SD24_B converter-2 bit stream data input/output (direction controlled by SD24_B)
Disables the output driver as well as the input Schmitt-trigger to prevent parasitic cross
currents when applying analog signals.
(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored
resulting in a read out value of 31.
Copyright © 2011–2012, Texas Instruments Incorporated
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