MSP430F673X Datasheet, PDF (37/121 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

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MSP430F673x
MSP430F672x
SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
Table 32. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
System control
Bootstrap loader configuration area
JTAG mailbox control
JTAG mailbox input 0
JTAG mailbox input 1
JTAG mailbox output 0
JTAG mailbox output 1
Bus Error vector generator
User NMI vector generator
System NMI vector generator
Reset vector generator
REGISTER
SYSCTL
SYSBSLC
SYSJMBC
SYSJMBI0
SYSJMBI1
SYSJMBO0
SYSJMBO1
SYSBERRIV
SYSUNIV
SYSSNIV
SYSRSTIV
OFFSET
00h
02h
06h
08h
0Ah
0Ch
0Eh
18h
1Ah
1Ch
1Eh
Table 33. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
Shared reference control
REGISTER
REFCTL
00h
OFFSET
Table 34. Port Mapping Controller (Base Address: 01C0h)
REGISTER DESCRIPTION
Port mapping password register
Port mapping control register
REGISTER
PMAPPWD
PMAPCTL
OFFSET
00h
02h
Table 35. Port Mapping for Port P1 (Base Address: 01C8h)
REGISTER DESCRIPTION
Port P1.0 mapping register
Port P1.1 mapping register
Port P1.2 mapping register
Port P1.3 mapping register
Port P1.4 mapping register
Port P1.5 mapping register
Port P1.6 mapping register
Port P1.7 mapping register
REGISTER
P1MAP0
00h
P1MAP1
01h
P1MAP2
02h
P1MAP3
03h
P1MAP4
04h
P1MAP5
05h
P1MAP6
06h
P1MAP7
07h
OFFSET
Table 36. Port Mapping for Port P2 (Base Address: 01D0h)
REGISTER DESCRIPTION
Port P2.0 mapping register
Port P2.1 mapping register
Port P2.2 mapping register
Port P2.3 mapping register
Port P2.4 mapping register
Port P2.5 mapping register
Port P2.6 mapping register
Port P2.7 mapping register
REGISTER
P2MAP0
00h
P2MAP2
01h
P2MAP2
02h
P2MAP3
03h
P2MAP4
04h
P2MAP5
05h
P2MAP6
06h
P2MAP7
07h
OFFSET
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