MSP430F677X1_16 Datasheet, PDF (76/162 Pages) Texas Instruments – Polyphase Metering SoCs

MSP430F677x1, MSP430F676x1, MSP430F674x1
SLAS815C – NOVEMBER 2012 – REVISED DECEMBER 2013
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eUSCI (SPI Master Mode) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾
t_HD,MI
PARAMETER
SOMI input data hold time
TEST CONDITIONS
V_CC
MIN TYP
2V
0
3V
0
t_VALID,MO SIMO output data valid time⁽²⁾
UCLK edge to SIMO valid,
C_L = 20 pF
2V
3V
t_HD,MO
SIMO output data hold time⁽³⁾
C_L = 20 pF
2V
0
3V
0
MAX UNIT
ns
9
ns
5
ns
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 13 and Figure 14.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in
Figure 13 and Figure 14.
UCMODEx = 01
STE
UCMODEx = 10
UCLK
CKPL = 0
CKPL = 1
SOMI
t_STE,LEAD
1/f_UCxCLK
t_LOW/HIGH
t_LOW/HIGH
t_STE,LAG
t_SU,MI
t_HD,MI
SIMO
t_STE,ACC
t_VALID,MO
Figure 13. SPI Master Mode, CKPH = 0
t_STE,DIS
76
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