MSP430F677X1_16 Datasheet, PDF (4/162 Pages) Texas Instruments – Polyphase Metering SoCs

MSP430F677x1, MSP430F676x1, MSP430F674x1
SLAS815C – NOVEMBER 2012 – REVISED DECEMBER 2013
www.ti.com
Family members available are summarized in Table 1.
Table 1. Family Members⁽¹⁾⁽²⁾
Device
Flash
(KB)
MSP430F67791IPEU
512
MSP430F67781IPEU
512
MSP430F67771IPEU
256
MSP430F67761IPEU
256
MSP430F67751IPEU
128
MSP430F67691IPEU
512
MSP430F67681IPEU
512
MSP430F67671IPEU
256
MSP430F67661IPEU
256
MSP430F67651IPEU
128
MSP430F67491IPEU
512
MSP430F67481IPEU
512
MSP430F67471IPEU
256
MSP430F67461IPEU
256
MSP430F67451IPEU
128
MSP430F67791IPZ
512
MSP430F67781IPZ
512
MSP430F67771IPZ
256
MSP430F67761IPZ
256
MSP430F67751IPZ
128
MSP430F67691IPZ
512
MSP430F67681IPZ
512
MSP430F67671IPZ
256
MSP430F67661IPZ
256
MSP430F67651IPZ
128
MSP430F67491IPZ
512
MSP430F67481IPZ
512
MSP430F67471IPZ
256
MSP430F67461IPZ
256
MSP430F67451IPZ
128
SRAM
(KB)
SD24_B
Converters
ADC10_A
Channels
32
7
6 ext, 2 int
16
7
6 ext, 2 int
32
7
6 ext, 2 int
16
7
6 ext, 2 int
16
7
6 ext, 2 int
32
6
6 ext, 2 int
16
6
6 ext, 2 int
32
6
6 ext, 2 int
16
6
6 ext, 2 int
16
6
6 ext, 2 int
32
4
6 ext, 2 int
16
4
6 ext, 2 int
32
4
6 ext, 2 int
16
4
6 ext, 2 int
16
4
6 ext, 2 int
32
7
6 ext, 2 int
16
7
6 ext, 2 int
32
7
6 ext, 2 int
16
7
6 ext, 2 int
16
7
6 ext, 2 int
32
6
6 ext, 2 int
16
6
6 ext, 2 int
32
6
6 ext, 2 int
16
6
6 ext, 2 int
16
6
6 ext, 2 int
32
4
6 ext, 2 int
16
4
6 ext, 2 int
32
4
6 ext, 2 int
16
4
6 ext, 2 int
16
4
6 ext, 2 int
Timer_A ⁽³⁾
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
eUSCI
Channel A: Channel B:
I/O
UART, IrDA, SPI, I²C
SPI
4
2
90
4
2
90
4
2
90
4
2
90
4
2
90
4
2
90
4
2
90
4
2
90
4
2
90
4
2
90
4
2
90
4
2
90
4
2
90
4
2
90
4
2
90
4
2
62
4
2
62
4
2
62
4
2
62
4
2
62
4
2
62
4
2
62
4
2
62
4
2
62
4
2
62
4
2
62
4
2
62
4
2
62
4
2
62
4
2
62
Package
Type
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
4
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