MSP430F677X1_16 Datasheet, PDF (22/162 Pages) Texas Instruments – Polyphase Metering SoCs

MSP430F677x1, MSP430F676x1, MSP430F674x1
SLAS815C – NOVEMBER 2012 – REVISED DECEMBER 2013
Table 5. Terminal Functions – PZ Package (continued)
TERMINAL
NAME
NO. I/O⁽¹⁾
PZ
DESCRIPTION
P8.0/S0
93 I/O ^{General-purpose digital I/O}
LCD segment output S0
General-purpose digital I/O
P8.1/TACLK/RTCCLK/CB3 94 I/O ^{Timer clock input TACLK for TA0, TA1, TA2, TA3}
RTCCLK clock output
Comparator_B input CB3
TEST/SBWTCK
95
I ^{Test mode pin – select digital I/O on JTAG pins}
Spy-By-Wire input clock
PJ.0/TDO
96 I/O ^{General-purpose digital I/O}
Test data output
PJ.1/TDI/TCLK
97 I/O ^{General-purpose digital I/O}
Test data input or Test clock input
PJ.2/TMS
98 I/O ^{General-purpose digital I/O}
Test mode select
PJ.3/TCK
RST/NMI/SBWTDIO
99 I/O ^{General-purpose digital I/O}
Test clock
Reset input active low⁽⁶⁾
100 I/O _{Non-maskable interrupt input}
Spy-By-Wire data input/output
(6) When this pin is configured as reset, the internal pullup resistor is enabled by default.
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