MSP430F677X1_16 Datasheet, PDF (34/162 Pages) Texas Instruments – Polyphase Metering SoCs

MSP430F677x1, MSP430F676x1, MSP430F674x1
SLAS815C – NOVEMBER 2012 – REVISED DECEMBER 2013
www.ti.com
Auxiliary Supply System (Link to User's Guide)
The auxiliary supply system provides the option to operate the device from auxiliary supplies when the primary
supply fails. There are two auxiliary supplies (AUXVCC1 and AUXVCC2) supported in MSP430F67xx. This
module supports automatic and manual switching from primary supply to auxiliary supplies while maintaining full
functionality. It allows threshold-based monitoring of primary and auxiliary supplies. The device can be started
from primary supply or AUXVCC1, whichever is higher. Auxiliary supply system enables internal monitoring of
voltage levels on primary and auxiliary supplies using ADC10_A. This module also implements a simple charger
for backup capacitors.
Backup Subsystem (Link to User's Guide)
The Backup subsystem operates on a dedicated power supply AUXVCC3. This subsystem includes low-
frequency oscillator, Real-Time Clock module, and Backup RAM. The functionality of Backup subsystem is
retained during LPM3.5. The Backup subsystem module registers cannot be accessed by CPU when the high
side SVS is disabled by user.
Digital I/O (Link to User's Guide)
There are up to eleven 8-bit I/O ports implemented. For 128-pin options, Ports P1 to P10 are complete, and Port
P11 is 6 bits wide. For 100-pin options, Ports P1 to P7 are complete, Port P8 is 2 bits wide, and ports P9, P10,
and P11 are completely removed. Port PJ contains four individual I/O pins, common to all devices. All I/O bits are
individually programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Programmable drive strength on all ports.
• Edge-selectable interrupt and LPM3.5, LPM4.5 wakeup input capability available for all bits of ports P1 and
P2.
• Read-write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise (P1 Through P11) or word-wise in pairs (PA Through PF).
Port Mapping Controller (Link to User's Guide)
The port mapping controller allows flexible and reconfigurable mapping of digital functions to Ports P2, P3, and
P4.
VALUE
0
1
2
3
4
5
6
7
8
9
10
11
Table 15. Port Mapping Mnemonics and Functions
PxMAPy MNEMONIC
PM_NONE
PM_UCA0RXD
PM_UCA0SOMI
PM_UCA0TXD
PM_UCA0SIMO
PM_UCA0CLK
PM_UCA0STE
PM_UCA1RXD
PM_UCA1SOMI
PM_UCA1TXD
PM_UCA1SIMO
PM_UCA1CLK
PM_UCA1STE
PM_UCA2RXD
PM_UCA2SOMI
PM_UCA2TXD
PM_ UCA2SIMO
PM_UCA2CLK
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
None
DVSS
eUSCI_A0 UART RXD (direction controlled by eUSCI – Input)
eUSCI_A0 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A0 UART TXD (direction controlled by eUSCI – Output)
eUSCI_A0 SPI slave in master out (direction controlled by eUSCI)
eUSCI_A0 clock input/output (direction controlled by eUSCI)
eUSCI_A0 SPI slave transmit enable (direction controlled by eUSCI)
eUSCI_A1 UART RXD (direction controlled by eUSCI – Input)
eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A1 UART TXD (direction controlled by eUSCI – Output)
eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)
eUSCI_A1 clock input/output (direction controlled by eUSCI)
eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI)
eUSCI_A2 UART RXD (direction controlled by eUSCI – Input)
eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A2 UART TXD (direction controlled by eUSCI – Output)
eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)
eUSCI_A2 clock input/output (direction controlled by eUSCI)
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