MSP430F677X1_16 Datasheet, PDF (36/162 Pages) Texas Instruments – Polyphase Metering SoCs

MSP430F677x1, MSP430F676x1, MSP430F674x1
SLAS815C – NOVEMBER 2012 – REVISED DECEMBER 2013
www.ti.com
Table 16. Default Port Mapping (continued)
PIN NAME
PEU
PZ
P3.5/PM_UCA1TXD/
PM_UCA1SIMO
P3.5/PM_UCA1TXD/
PM_UCA1SIMO/S35
P3.6/PM_UCA2RXD/
PM_UCA2SOMI/
P3.6/PM_UCA2RXD/
PM_UCA2SOMI/S34
P3.7/PM_UCA2TXD/
PM_UCA2SIMO
P3.7/PM_UCA2TXD/
PM_UCA2SIMO/S33
P4.0/PM_UCA2CLK
P4.0/PM_UCA2CLK/S32
P4.1/PM_UCA3RXD/
PM_UCA3SOMI/
P4.1/PM_UCA3RXD/
PM_UCA3SOMI/S31
P4.2/PM_UCA3TXD/
PM_UCA3SIMO
P4.2/PM_UCA3TXD/
PM_UCA3SIMO/S30
P4.3/PM_UCA3CLK
P4.3/PM_UCA3CLK/S29
P4.4/PM_UCB1SOMI/
PM_UCB1SCL
P4.4/PM_UCB1SOMI/
PM_UCB1SCL/S28
P4.5/PM_UCB1SIMO/
PM_UCB1SDA
P4.5/PM_UCB1SIMO/
PM_UCB1SDA/S27
P4.6/PM_UCB1CLK
P4.6/PM_UCB1CLK/S26
P4.7/PM_TA3.0
P4.7/PM_TA3.0/S25
PxMAPy
MNEMONIC
PM_UCA1TXD/
PM_UCA1SIMO
PM_UCA2RXD/
PM_UCA2SOMI
PM_UCA2TXD/
PM_UCA2SIMO
PM_UCA2CLK
PM_UCA3RXD/
PM_UCA3SOMI
PM_UCA3TXD/
PM_UCA3SIMO
PM_UCA3CLK
PM_UCB1SOMI/
PM_UCB1SCL
PM_UCB1SIMO/
PM_UCB1SDA
PM_UCB1CLK
PM_TA3.0
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
eUSCI_A1 UART TXD (direction controlled by eUSCI – output),
eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)
eUSCI_A2 UART RXD (direction controlled by eUSCI – input),
eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A2 UART TXD (direction controlled by eUSCI – output),
eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)
eUSCI_A2 clock input/output (direction controlled by eUSCI)
eUSCI_A3 UART RXD (direction controlled by eUSCI – input),
eUSCI_A3 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A3 UART TXD (direction controlled by eUSCI – output),
eUSCI_A3 SPI slave in master out (direction controlled by eUSCI)
eUSCI_A3 clock input/output (direction controlled by eUSCI)
eUSCI_B1 SPI slave out master in (direction controlled by eUSCI),
eUSCI_B1 I2C clock (open drain and direction controlled by eUSCI)
eUSCI_B1 SPI slave in master out (direction controlled by eUSCI),
eUSCI_B1 I2C data (open drain and direction controlled by eUSCI)
eUSCI_B1 clock input/output (direction controlled by eUSCI)
TA3 CCR0 capture input CCI0A
TA3 CCR0 compare output Out0
System Module (SYS) (Link to User's Guide)
The SYS module handles many of the system functions within the device. These include power on reset and
power up clear handling, NMI source selection and management, reset interrupt vector generators, bootstrap
loader entry mechanisms, and configuration management (device descriptors). It also includes a data exchange
mechanism using JTAG called a JTAG mailbox that can be used in the application.
Table 17. System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTER
SYSRSTIV , System Reset
ADDRESS
019Eh
SYSSNIV , System NMI
019Ch
INTERRUPT EVENT
No interrupt pending
Brownout (BOR)
RST/NMI (POR)
DoBOR (BOR)
Wakeup from LPMx.5
Security violation (BOR)
SVSL (POR)
SVSH (POR)
SVML_OVP (POR)
SVMH_OVP (POR)
DoPOR (POR)
WDT timeout (PUC)
WDT key violation (PUC)
KEYV flash key violation (PUC)
Reserved
Peripheral area fetch (PUC)
PMM key violation (PUC)
Reserved
No interrupt pending
SVMLIFG
SVMHIFG
DLYLIFG
DLYHIFG
VALUE
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h to 3Eh
00h
02h
04h
06h
08h
PRIORITY
Highest
Lowest
Highest
36
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated