MSP430F677X1_16 Datasheet, PDF (28/162 Pages) Texas Instruments – Polyphase Metering SoCs

MSP430F677x1, MSP430F676x1, MSP430F674x1
SLAS815C – NOVEMBER 2012 – REVISED DECEMBER 2013
www.ti.com
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 8. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
System Reset
Power-Up
External Reset
Watchdog Timeout, Key Violation
Flash Memory Key Violation
System NMI
PMM
Vacant Memory Access
JTAG Mailbox
User NMI
NMI
Oscillator Fault
Flash Memory Access Violation
Supply Switched
Watchdog Timer_A Interval Timer
Mode
eUSCI_A0 Receive or Transmit
eUSCI_B0 Receive or Transmit
ADC10_A
SD24_B
Timer TA0
Timer TA0
eUSCI_A1 Receive or Transmit
eUSCI_A2 Receive or Transmit
Auxiliary Supplies
DMA
Timer TA1
Timer TA1
eUSCI_A3 Receive or Transmit
eUSCI_B1 Receive or Transmit
I/O Port P1
Timer TA2
Timer TA2
I/O Port P2
Timer TA3
Timer TA3
LCD_C
RTC_C
WDTIFG, KEYV (SYSRSTIV)^{(1) (2)}
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,
JMBOUTIFG (SYSSNIV) ^{(1) (3)}
NMIIFG, OFIFG, ACCVIFG, AUXSWGIFG
(SYSUNIV)^{(1) (3)}
WDTIFG
UCA0RXIFG, UCA0TXIFG (UCA0IV) ^{(1) (4)}
UCB0RXIFG, UCB0TXIFG (UCB0IV) ^{(1) (4)}
ADC10IFG0, ADC10INIFG, ADC10LOIFG,
ADC10HIIFG, ADC10TOVIFG, ADC10OVIFG
(ADC10IV)^{(1) (4)}
SD24_B Interrupt Flags (SD24IV)^{(1) (4)}
TA0CCR0 CCIFG0⁽⁴⁾
TA0CCR1 CCIFG1, TA0CCR2 CCIFG2,
TA0IFG (TA0IV)^{(1) (4)}
UCA1RXIFG, UCA1TXIFG (UCA1IV) ^{(1) (4)}
UCA2RXIFG, UCA2TXIFG (UCA2IV) ^{(1) (4)}
AUXSWGIFG, AUXIFG0, AUXIFG1, AUXIFG2
(AUXIV)^{(1) (4)}
DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)^{(1) (4)}
TA1CCR0 CCIFG0⁽⁴⁾
TA1CCR1 CCIFG1,
TA1IFG (TA1IV)^{(1) (4)}
UCA3RXIFG, UCA3TXIFG (UCA3IV) ^{(1) (4)}
UCB1RXIFG, UCB1TXIFG (UCB1IV) ^{(1) (4)}
P1IFG.0 to P1IFG.7 (P1IV) ^{(1) (4)}
TA2CCR0 CCIFG0⁽⁴⁾
TA2CCR1 CCIFG1,
TA2IFG (TA2IV)^{(1) (4)}
P2IFG.0 to P2IFG.7 (P2IV) ^{(1) (4)}
TA3CCR0 CCIFG0⁽⁴⁾
TA3CCR1 CCIFG1,
TA3IFG (TA3IV)^{(1) (4)}
LCD_C Interrupt Flags (LCDCIV)^{(1) (4)}
RTCOFIFG, RTCRDYIFG, RTCTEVIFG,
RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV) ^{(1) (4)}
SYSTEM
INTERRUPT
Reset
(Non)maskable
(Non)maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
WORD
ADDRESS
PRIORITY
0FFFEh
63, highest
0FFFCh
62
0FFFAh
61
0FFF8h
60
0FFF6h
59
0FFF4h
58
0FFF2h
57
0FFF0h
56
0FFEEh
55
0FFECh
54
0FFEAh
53
0FFE8h
52
0FFE6h
51
0FFE4h
50
0FFE2h
49
0FFE0h
48
0FFDEh
47
0FFDCh
46
0FFDAh
45
0FFD8h
44
0FFD6h
43
0FFD4h
42
0FFD2h
41
0FFD0h
40
0FFCEh
39
0FFCCh
38
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(3) (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(4) Interrupt flags are located in the module.
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