MSP430F677X1_16 Datasheet, PDF (75/162 Pages) Texas Instruments – Polyphase Metering SoCs

MSP430F677x1, MSP430F676x1, MSP430F674x1
www.ti.com
SLAS815C – NOVEMBER 2012 – REVISED DECEMBER 2013
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Internal: SMCLK or ACLK,
f_TA
Timer_A input clock frequency
External: TACLK,
Duty cycle = 50% ± 10%
V_CC
1.8 V, 3 V
MIN TYP
t_TA,cap
Timer_A capture timing
All capture inputs.
Minimum pulse duration required for 1.8 V, 3 V
20
capture.
MAX UNIT
25 MHz
ns
eUSCI (UART Mode) Recommended Operating Conditions
PARAMETER
CONDITIONS
f_eUSCI
eUSCI input clock frequency
Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ± 10%
f_BITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
V_CC
MIN TYP MAX UNIT
f_SYSTEM MHz
5 MHz
eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UCGLITx = 0
V_CC
MIN TYP
10
15
t_t
UART receive deglitch time⁽¹⁾
UCGLITx = 1
UCGLITx = 2
2 V, 3 V
30
50
50
80
UCGLITx = 3
70 120
MAX
25
85
150
200
UNIT
ns
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To make sure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
eUSCI (SPI Master Mode) Recommended Operating Conditions
PARAMETER
CONDITIONS
V_CC
f_eUSCI
eUSCI input clock frequency
Internal: SMCLK or ACLK,
Duty cycle = 50% ± 10%
MIN TYP MAX UNIT
f_SYSTEM MHz
eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾
t_STE,LEAD
PARAMETER
STE lead time, STE low to clock
TEST CONDITIONS
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
V_CC
2 V, 3 V
2 V, 3 V
MIN TYP
150
150
t_STE,LAG
STE lag time, Last clock to STE ^{UCSTEM = 0, UCMODEx = 01 or 10}
high
UCSTEM = 1, UCMODEx = 01 or 10
2 V, 3 V
200
2 V, 3 V
200
2V
UCSTEM = 0, UCMODEx = 01 or 10
t_STE,ACC
STE access time, STE low to
SIMO data out
3V
2V
UCSTEM = 1, UCMODEx = 01 or 10
3V
2V
UCSTEM = 0, UCMODEx = 01 or 10
t_STE,DIS
STE disable time, STE high to
SIMO high impedance
3V
2V
UCSTEM = 1, UCMODEx = 01 or 10
3V
t_SU,MI
SOMI input data setup time
2V
50
3V
30
MAX UNIT
ns
ns
50
30
ns
50
30
40
25
ns
40
25
ns
(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI = max(t_{VALID,MO(eUSCI)} + t_SU,SI(Slave), t_SU,MI(eUSCI) + t_{VALID,SO(Slave)}).
For the slave's parameters t_SU,SI(Slave) and t_{VALID,SO(Slave)} see the SPI parameters of the attached slave.
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