LM3S2776 Datasheet, PDF (716/785 Pages) Texas Instruments – Stellaris® LM3S2776 Microcontroller

Signal Tables
Table 19-3. Signals by Function, Except for GPIO (continued)
Function
Pin Name Pin Number Pin Type Buffer Type^a
Description
Fault0
8
I
TTL
PWM Fault 0.
Fault1
56
I
TTL
PWM Fault 1.
Fault2
14
I
TTL
PWM Fault 2.
PWM0
61
O
TTL
PWM 0. This signal is controlled by PWM Generator
0.
PWM1
62
O
TTL
PWM 1. This signal is controlled by PWM Generator
0.
PWM
PWM2
PWM3
41
O
TTL
PWM 2. This signal is controlled by PWM Generator
1.
42
O
TTL
PWM 3. This signal is controlled by PWM Generator
1.
PWM4
25
O
TTL
PWM 4. This signal is controlled by PWM Generator
2.
PWM5
26
O
TTL
PWM 5. This signal is controlled by PWM Generator
2.
PWM6
11
O
TTL
PWM 6. This signal is controlled by PWM Generator
3.
PWM7
15
O
TTL
PWM 7. This signal is controlled by PWM Generator
3.
GND
10
-
Power Ground reference for logic and I/O pins.
13
24
29
36
39
44
53
60
GNDA
4
-
Power The ground reference for the analog circuits (ADC,
etc.). These are separated from GND to minimize
the electrical noise contained on VDD from affecting
the analog functions.
LDO
Power
7
-
Power Low drop-out regulator output voltage. This pin
requires an external capacitor between the pin and
GND of 1 µF or greater. When the on-chip LDO is
used to provide power to the logic, the LDO pin must
also be connected to the VDD25 pins at the board
level in addition to the decoupling capacitor(s).
VDD
12
-
Power Positive supply for I/O and some logic.
28
43
59
VDD25
9
-
Power Positive supply for most of the logic function,
23
including the processor core and most peripherals.
38
54
VDDA
3
-
Power The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V,
regardless of system implementation.
716
November 17, 2011
Texas Instruments-Production Data