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LM3S2776 Datasheet, PDF (29/785 Pages) Texas Instruments – Stellaris® LM3S2776 Microcontroller | |||
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Stellaris® LM3S2776 Microcontroller
Table 1. Revision History (continued)
Date
October 2009
Revision
6449
Description
â Removed the MAXADCSPD bit field from the DCGC0 register as it has no function in deep-sleep
mode.
â Deleted reset value for 16-bit mode from GPTMTAILR, GPTMTAMATCHR, and GPTMTAR registers
because the module resets in 32-bit mode.
â Clarified CAN bit timing and corrected examples.
â Clarified PWM source for ADC triggering
â Made these changes to the Electrical Characteristics chapter:
â Removed VSIH and VSIL parameters from Operating Conditions table.
â Changed SSI set up and hold times to be expressed in system clocks, not ns.
â Revised ADC electrical specifications to clarify, including reorganizing and adding new data.
â Changed the name of the tHIB_REG_WRITE parameter to tHIB_REG_ACCESS.
â Table added showing actual PLL frequency depending on input crystal.
â Additional minor data sheet clarifications and corrections.
July 2009
5920
â Clarified Power-on reset and RST pin operation; added new diagrams.
â Corrected the reset value of the Hibernation Data (HIBDATA) and Hibernation Control (HIBCTL)
registers.
â Clarified explanation of nonvolatile register programming in Internal Memory chapter.
â Added explanation of reset value to FMPRE0/1/2/3, FMPPE0/1/2/3, USER_DBG, and USER_REG0/1
registers.
â Changed buffer type for WAKE pin to TTL.
â In ADC characteristics table, changed Max value for GAIN parameter from ±1 to ±3 and added
EIR(Internal voltage reference error) parameter.
â Changed ordering numbers.
â Additional minor data sheet clarifications and corrections.
April 2009
5368
â Added JTAG/SWD clarification (see âCommunication with JTAG/SWDâ on page 164).
â Added clarification that the PLL operates at 400 MHz, but is divided by two prior to the application
of the output divisor.
â Corrected bits 2:1 in I2CSIMR, I2CSRIS, I2CSMIS, and I2CSICR registers to be reserved bits
(cannot interrupt on start and stop conditions).
â Corrected bits 15:11 in USBTXMAXP0/1/2 and USBRXMAXP0/1/2 registers to be reserved bits
(cannot define multiplier).
â Additional minor data sheet clarifications and corrections.
November 17, 2011
29
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