LM3S2776 Datasheet, PDF (176/785 Pages) Texas Instruments – Stellaris® LM3S2776 Microcontroller

System Control
5.2.5.2
The internal system clock (SysClk), is derived from any of the above sources plus two others: the
output of the main internal PLL, and the internal oscillator divided by four (3 MHz ± 30%). The
frequency of the PLL clock reference must be in the range of 3.579545 MHz to 16.384 MHz
(inclusive). Table 5-3 on page 176 shows how the various clock sources can be used in a system.
Table 5-3. Clock Source Options
Clock Source
Internal Oscillator (12 MHz)
Internal Oscillator divide by 4 (3
MHz)
Main Oscillator
Internal 30-kHz Oscillator
External Real-Time Oscillator
Drive PLL?
No
BYPASS = 1
No
BYPASS = 1
Used as SysClk?
Yes
BYPASS = 1, OSCSRC = 0x1
Yes
BYPASS = 1, OSCSRC = 0x2
Yes
BYPASS = 0, OSCSRC = Yes
0x0
No
BYPASS = 1
Yes
No
BYPASS = 1
Yes
BYPASS = 1, OSCSRC = 0x0
BYPASS = 1, OSCSRC = 0x3
BYPASS = 1, OSCSRC2 = 0x7
Clock Configuration
The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2)
registers provide control for the system clock. The RCC2 register is provided to extend fields that
offer additional encodings over the RCC register. When used, the RCC2 register field values are
used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for
a larger assortment of clock configuration options. These registers control the following clock
functionality:
■ Source of clocks in sleep and deep-sleep modes
■ System clock derived from PLL or other clock source
■ Enabling/disabling of oscillators and PLL
■ Clock divisors
■ Crystal input selection
Figure 5-4 on page 177 shows the logic for the main clock tree. The peripheral blocks are driven by
the system clock signal and can be individually enabled/disabled. The ADC clock signal is
automatically divided down to 16 MHz for proper ADC operation. The PWM clock signal is a
synchronous divide of the system clock to provide the PWM circuit with more range (set with PWMDIV
in RCC).
Note: When the ADC module is in operation, the system clock must be at least 16 MHz.
176
November 17, 2011
Texas Instruments-Production Data