LM3S2776 Datasheet, PDF (709/785 Pages) Texas Instruments – Stellaris® LM3S2776 Microcontroller

Stellaris® LM3S2776 Microcontroller
19 Signal Tables
The following tables list the signals available for each pin. Functionality is enabled by software with
the GPIOAFSEL register.
Important: All multiplexed pins are GPIOs by default, with the exception of the four JTAG pins
(PC[3:0]) which default to the JTAG functionality.
Table 19-1 on page 709 shows the pin-to-signal-name mapping, including functional characteristics
of the signals. Table 19-2 on page 712 lists the signals in alphabetical order by signal name.
Table 19-3 on page 715 groups the signals by functionality, except for GPIOs. Table 19-4 on page 717
lists the GPIO pins and their alternate functionality.
Note: All digital inputs are Schmitt triggered.
Table 19-1. Signals by Pin Number
Pin Number
1
2
Pin Name
PE3
ADC0
PE2
ADC1
VDDA
Pin Type
I/O
I
I/O
I
-
3
GNDA
-
4
PE1
I/O
5
ADC2
I
PE0
I/O
6
ADC3
I
LDO
-
7
PE4
I/O
8
Fault0
I
9
VDD25
-
10
GND
-
PC4
I/O
11
PWM6
O
12
VDD
-
13
GND
-
PC5
I/O
14
Fault2
I
Buffer Type^a Description
TTL
GPIO port E bit 3.
Analog Analog-to-digital converter input 0.
TTL
GPIO port E bit 2.
Analog Analog-to-digital converter input 1.
Power
The positive supply (3.3 V) for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V, regardless of
system implementation.
Power
The ground reference for the analog circuits (ADC, etc.). These
are separated from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
TTL
GPIO port E bit 1.
Analog Analog-to-digital converter input 2.
TTL
GPIO port E bit 0.
Analog Analog-to-digital converter input 3.
Power
Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 µF or greater. When the
on-chip LDO is used to provide power to the logic, the LDO pin
must also be connected to the VDD25 pins at the board level in
addition to the decoupling capacitor(s).
TTL
GPIO port E bit 4.
TTL
PWM Fault 0.
Power
Positive supply for most of the logic function, including the
processor core and most peripherals.
Power Ground reference for logic and I/O pins.
TTL
GPIO port C bit 4.
TTL
PWM 6. This signal is controlled by PWM Generator 3.
Power Positive supply for I/O and some logic.
Power Ground reference for logic and I/O pins.
TTL
GPIO port C bit 5.
TTL
PWM Fault 2.
November 17, 2011
709
Texas Instruments-Production Data