LM3S2776 Datasheet, PDF (5/785 Pages) Texas Instruments – Stellaris® LM3S2776 Microcontroller

Stellaris® LM3S2776 Microcontroller
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6.1
6.2
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.5
6.6
Hibernation Module .............................................................................................. 236
Block Diagram ............................................................................................................ 237
Signal Description ....................................................................................................... 237
Functional Description ................................................................................................. 238
Register Access Timing ............................................................................................... 238
Clock Source .............................................................................................................. 238
Battery Management ................................................................................................... 240
Real-Time Clock .......................................................................................................... 240
Battery-Backed Memory .............................................................................................. 240
Power Control ............................................................................................................. 241
Initiating Hibernate ...................................................................................................... 241
Interrupts and Status ................................................................................................... 241
Initialization and Configuration ..................................................................................... 242
Initialization ................................................................................................................. 242
RTC Match Functionality (No Hibernation) .................................................................... 242
RTC Match/Wake-Up from Hibernation ......................................................................... 242
External Wake-Up from Hibernation .............................................................................. 243
RTC/External Wake-Up from Hibernation ...................................................................... 243
Register Map .............................................................................................................. 243
Register Descriptions .................................................................................................. 244
7
7.1
7.2
7.2.1
7.2.2
7.2.3
7.3
7.3.1
7.3.2
7.4
7.5
7.6
7.7
Internal Memory ................................................................................................... 258
Block Diagram ............................................................................................................ 258
Functional Description ................................................................................................. 258
SRAM Memory ............................................................................................................ 258
ROM Memory ............................................................................................................. 259
Flash Memory ............................................................................................................. 259
Flash Memory Initialization and Configuration ............................................................... 261
Flash Programming ..................................................................................................... 261
Nonvolatile Register Programming ............................................................................... 261
Register Map .............................................................................................................. 262
ROM Register Descriptions (System Control Offset) ...................................................... 263
Flash Register Descriptions (Flash Control Offset) ......................................................... 264
Flash Register Descriptions (System Control Offset) ...................................................... 272
8
Micro Direct Memory Access (μDMA) ................................................................ 287
8.1 Block Diagram ............................................................................................................ 288
8.2 Functional Description ................................................................................................. 288
8.2.1 Channel Assigments .................................................................................................... 289
8.2.2 Priority ........................................................................................................................ 289
8.2.3 Arbitration Size ............................................................................................................ 289
8.2.4 Request Types ............................................................................................................ 289
8.2.5 Channel Configuration ................................................................................................. 290
8.2.6 Transfer Modes ........................................................................................................... 292
8.2.7 Transfer Size and Increment ........................................................................................ 300
8.2.8 Peripheral Interface ..................................................................................................... 300
8.2.9 Software Request ........................................................................................................ 300
8.2.10 Interrupts and Errors .................................................................................................... 301
8.3 Initialization and Configuration ..................................................................................... 301
8.3.1 Module Initialization ..................................................................................................... 301
November 17, 2011
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